/*\r
- FreeRTOS V9.0.0rc2 - Copyright (C) 2016 Real Time Engineers Ltd.\r
+ FreeRTOS V9.0.1 - Copyright (C) 2017 Real Time Engineers Ltd.\r
All rights reserved\r
\r
VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
\r
#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE\r
\r
+#ifndef configSYSTICK_CLOCK_HZ\r
+ #define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ\r
+ /* Ensure the SysTick is clocked at the same frequency as the core. */\r
+ #define portNVIC_SYSTICK_CLK ( 1UL << 2UL )\r
+#else\r
+ /* The way the SysTick is clocked is not modified in case it is not the same\r
+ as the core. */\r
+ #define portNVIC_SYSTICK_CLK ( 0 )\r
+#endif\r
+\r
/* Constants required to access and manipulate the NVIC. */\r
#define portNVIC_SYSTICK_CTRL_REG ( * ( ( volatile uint32_t * ) 0xe000e010 ) )\r
#define portNVIC_SYSTICK_LOAD_REG ( * ( ( volatile uint32_t * ) 0xe000e014 ) )\r
+#define portNVIC_SYSTICK_CURRENT_VALUE_REG ( * ( ( volatile uint32_t * ) 0xe000e018 ) )\r
#define portNVIC_SYSPRI2_REG ( * ( ( volatile uint32_t * ) 0xe000ed20 ) )\r
#define portNVIC_SYSPRI1_REG ( * ( ( volatile uint32_t * ) 0xe000ed1c ) )\r
#define portNVIC_SYS_CTRL_STATE_REG ( * ( ( volatile uint32_t * ) 0xe000ed24 ) )\r
#define portPERIPHERALS_END_ADDRESS 0x5FFFFFFFUL\r
\r
/* Constants required to access and manipulate the SysTick. */\r
-#define portNVIC_SYSTICK_CLK ( 0x00000004UL )\r
#define portNVIC_SYSTICK_INT ( 0x00000002UL )\r
#define portNVIC_SYSTICK_ENABLE ( 0x00000001UL )\r
#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )\r
have bit-0 clear, as it is loaded into the PC on exit from an ISR. */\r
#define portSTART_ADDRESS_MASK ( ( StackType_t ) 0xfffffffeUL )\r
\r
-/* Each task maintains its own interrupt status in the critical nesting\r
-variable. Note this is not saved as part of the task context as context\r
-switches can only occur when uxCriticalNesting is zero. */\r
-static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;\r
-\r
-/*\r
- * Setup the timer to generate the tick interrupts.\r
- */\r
-static void prvSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION;\r
-\r
/*\r
* Configure a number of standard MPU regions that are used by all tasks.\r
*/\r
*/\r
BaseType_t xPortRaisePrivilege( void ) __attribute__(( naked ));\r
\r
+/*\r
+ * Setup the timer to generate the tick interrupts. The implementation in this\r
+ * file is weak to allow application writers to change the timer used to\r
+ * generate the tick interrupt.\r
+ */\r
+void vPortSetupTimerInterrupt( void );\r
+\r
/*\r
* Standard FreeRTOS exception handlers.\r
*/\r
*/\r
static void prvSVCHandler( uint32_t *pulRegisters ) __attribute__(( noinline )) PRIVILEGED_FUNCTION;\r
\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Each task maintains its own interrupt status in the critical nesting\r
+variable. Note this is not saved as part of the task context as context\r
+switches can only occur when uxCriticalNesting is zero. */\r
+static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;\r
+\r
/*\r
* Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure\r
* FreeRTOS API functions are not called from interrupts that have been assigned\r
" mrs r0, psp \n"\r
#endif\r
" b %0 \n"\r
- ::"i"(prvSVCHandler):"r0"\r
+ ::"i"(prvSVCHandler):"r0", "memory"\r
);\r
}\r
/*-----------------------------------------------------------*/\r
but do ensure the code is completely\r
within the specified behaviour for the\r
architecture. */\r
- __asm volatile( "dsb" );\r
+ __asm volatile( "dsb" ::: "memory" );\r
__asm volatile( "isb" );\r
\r
break;\r
" mrs r1, control \n" /* Obtain current control value. */\r
" bic r1, #1 \n" /* Set privilege bit. */\r
" msr control, r1 \n" /* Write back new control value. */\r
- :::"r1"\r
+ ::: "r1", "memory"\r
);\r
break;\r
\r
ucMaxPriorityValue <<= ( uint8_t ) 0x01;\r
}\r
\r
+ #ifdef __NVIC_PRIO_BITS\r
+ {\r
+ /* Check the CMSIS configuration that defines the number of\r
+ priority bits matches the number of priority bits actually queried\r
+ from the hardware. */\r
+ configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS );\r
+ }\r
+ #endif\r
+\r
+ #ifdef configPRIO_BITS\r
+ {\r
+ /* Check the FreeRTOS configuration that defines the number of\r
+ priority bits matches the number of priority bits actually queried\r
+ from the hardware. */\r
+ configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );\r
+ }\r
+ #endif\r
+\r
/* Shift the priority group value back to its position within the AIRCR\r
register. */\r
ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;\r
\r
/* Start the timer that generates the tick ISR. Interrupts are disabled\r
here already. */\r
- prvSetupTimerInterrupt();\r
+ vPortSetupTimerInterrupt();\r
\r
/* Initialise the critical nesting count ready for the first task. */\r
uxCriticalNesting = 0;\r
\r
/* Start the first task. */\r
- __asm volatile( " svc %0 \n"\r
- :: "i" (portSVC_START_SCHEDULER) );\r
+ __asm volatile(\r
+ " ldr r0, =0xE000ED08 \n" /* Use the NVIC offset register to locate the stack. */\r
+ " ldr r0, [r0] \n"\r
+ " ldr r0, [r0] \n"\r
+ " msr msp, r0 \n" /* Set the msp back to the start of the stack. */\r
+ " cpsie i \n" /* Globally enable interrupts. */\r
+ " cpsie f \n"\r
+ " dsb \n"\r
+ " isb \n"\r
+ " svc %0 \n" /* System call to start first task. */\r
+ " nop \n"\r
+ :: "i" (portSVC_START_SCHEDULER) : "memory" );\r
\r
/* Should not get here! */\r
return 0;\r
" stmdb sp!, {r3, r14} \n"\r
" mov r0, %0 \n"\r
" msr basepri, r0 \n"\r
+ " dsb \n"\r
+ " isb \n"\r
" bl vTaskSwitchContext \n"\r
" mov r0, #0 \n"\r
" msr basepri, r0 \n"\r
* Setup the systick timer to generate the tick interrupts at the required\r
* frequency.\r
*/\r
-static void prvSetupTimerInterrupt( void )\r
+__attribute__(( weak )) void vPortSetupTimerInterrupt( void )\r
{\r
+ /* Stop and clear the SysTick. */\r
+ portNVIC_SYSTICK_CTRL_REG = 0UL;\r
+ portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\r
+\r
/* Configure SysTick to interrupt at the requested rate. */\r
- portNVIC_SYSTICK_LOAD_REG = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;\r
- portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE;\r
+ portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;\r
+ portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE );\r
}\r
/*-----------------------------------------------------------*/\r
\r
" svcne %0 \n" /* Switch to privileged. */\r
" moveq r0, #1 \n" /* CONTROL[0]==0, return true. */\r
" bx lr \n"\r
- :: "i" (portSVC_RAISE_PRIVILEGE) : "r0"\r
+ :: "i" (portSVC_RAISE_PRIVILEGE) : "r0", "memory"\r
);\r
\r
return 0;\r
uint8_t ucCurrentPriority;\r
\r
/* Obtain the number of the currently executing interrupt. */\r
- __asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) );\r
+ __asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) :: "memory" );\r
\r
/* Is the interrupt number a user defined interrupt? */\r
if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )\r
projects / freertos / blobdiff