* in use.\r
*\r
* + The code that tailors the kernel's RISC-V port to a specific RISC-V\r
- * chip is implemented in freertos_risc_v_port_specific_extensions.h. There\r
- * is one freertos_risc_v_port_specific_extensions.h that can be used with any\r
+ * chip is implemented in freertos_risc_v_chip_specific_extensions.h. There\r
+ * is one freertos_risc_v_chip_specific_extensions.h that can be used with any\r
* RISC-V chip that both includes a standard CLINT and does not add to the\r
* base set of RISC-V registers. There are additional\r
- * freertos_risc_v_port_specific_extensions.h files for RISC-V implementations\r
+ * freertos_risc_v_chip_specific_extensions.h files for RISC-V implementations\r
* that do not include a standard CLINT or do add to the base set of RISC-V\r
* registers.\r
*\r
* CARE MUST BE TAKEN TO INCLDUE THE CORRECT\r
- * freertos_risc_v_port_specific_extensions.h HEADER FILE FOR THE CHIP\r
- * IN USE. To include the correct freertos_risc_v_port_specific_extensions.h\r
+ * freertos_risc_v_chip_specific_extensions.h HEADER FILE FOR THE CHIP\r
+ * IN USE. To include the correct freertos_risc_v_chip_specific_extensions.h\r
* header file ensure the path to the correct header file is in the assembler's\r
* include path.\r
*\r
- * This freertos_risc_v_port_specific_extensions.h is for use on RISC-V chips\r
+ * This freertos_risc_v_chip_specific_extensions.h is for use on RISC-V chips\r
* that include a standard CLINT and do not add to the base set of RISC-V\r
* registers.\r
*\r
*/\r
-#include "freertos_risc_v_port_specific_extensions.h"\r
+#include "freertos_risc_v_chip_specific_extensions.h"\r
\r
-/* Check the freertos_risc_v_port_specific_extensions.h and/or command line\r
+/* Check the freertos_risc_v_chip_specific_extensions.h and/or command line\r
definitions. */\r
#ifndef portasmHAS_CLINT\r
- #error freertos_risc_v_port_specific_extensions.h must define portasmHAS_CLINT to either 1 (CLINT present) or 0 (clint not present).\r
+ #error freertos_risc_v_chip_specific_extensions.h must define portasmHAS_CLINT to either 1 (CLINT present) or 0 (clint not present).\r
#endif\r
\r
#ifndef portasmHANDLE_INTERRUPT\r
- #error portasmHANDLE_INTERRUPT must be defined to the function to be called to handle external/peripheral interrupts. portasmHANDLE_INTERRUPT can be defined on the assmbler command line or in the appropriate freertos_risc_v_port_specific_extensions.h header file.\r
+ #error portasmHANDLE_INTERRUPT must be defined to the function to be called to handle external/peripheral interrupts. portasmHANDLE_INTERRUPT can be defined on the assmbler command line or in the appropriate freertos_risc_v_chip_specific_extensions.h header file.\r
#endif\r
\r
/* Only the standard core registers are stored by default. Any additional\r
registers must be saved by the portasmSAVE_ADDITIONAL_REGISTERS and\r
portasmRESTORE_ADDITIONAL_REGISTERS macros - which can be defined in a chip\r
-specific version of freertos_risc_v_port_specific_extensions.h. See the notes\r
+specific version of freertos_risc_v_chip_specific_extensions.h. See the notes\r
at the top of this file. */\r
#define portCONTEXT_SIZE ( 30 * portWORD_SIZE )\r
\r
.global xPortStartFirstTask\r
-.global vFreeRTOSPortTrapHandler\r
+.global freertos_risc_v_trap_handler\r
.global pxPortInitialiseStack\r
.extern pxCurrentTCB\r
.extern ulPortTrapHandler\r
\r
.align 8\r
.func\r
-vFreeRTOSPortTrapHandler:\r
+freertos_risc_v_trap_handler:\r
addi sp, sp, -portCONTEXT_SIZE\r
sw x1, 1 * portWORD_SIZE( sp )\r
sw x5, 2 * portWORD_SIZE( sp )\r
csrr t0, mstatus /* Required for MPIE bit. */\r
sw t0, 29 * portWORD_SIZE( sp )\r
\r
- portasmSAVE_ADDITIONAL_REGISTERS /* Defined in freertos_risc_v_port_specific_extensions.h to save any registers unique to the RISC-V implementation. */\r
+ portasmSAVE_ADDITIONAL_REGISTERS /* Defined in freertos_risc_v_chip_specific_extensions.h to save any registers unique to the RISC-V implementation. */\r
\r
lw t0, pxCurrentTCB /* Load pxCurrentTCB. */\r
sw sp, 0( t0 ) /* Write sp to first TCB member. */\r
lw t0, 0( sp )\r
csrw mepc, t0\r
\r
- portasmRESTORE_ADDITIONAL_REGISTERS /* Defined in freertos_risc_v_port_specific_extensions.h to restore any registers unique to the RISC-V implementation. */\r
+ portasmRESTORE_ADDITIONAL_REGISTERS /* Defined in freertos_risc_v_chip_specific_extensions.h to restore any registers unique to the RISC-V implementation. */\r
\r
/* Load mstatus with the interrupt enable bits used by the task. */\r
lw t0, 29 * portWORD_SIZE( sp )\r
/* If there is a clint then interrupts can branch directly to the FreeRTOS\r
trap handler. Otherwise the interrupt controller will need to be configured\r
outside of this file. */\r
- la t0, vFreeRTOSPortTrapHandler\r
+ la t0, freertos_risc_v_trap_handler\r
csrw mtvec, t0\r
#endif /* portasmHAS_CLILNT */\r
\r
\r
lw x1, 0( sp ) /* Note for starting the scheduler the exception return address is used as the function return address. */\r
\r
- portasmRESTORE_ADDITIONAL_REGISTERS /* Defined in freertos_risc_v_port_specific_extensions.h to restore any registers unique to the RISC-V implementation. */\r
+ portasmRESTORE_ADDITIONAL_REGISTERS /* Defined in freertos_risc_v_chip_specific_extensions.h to restore any registers unique to the RISC-V implementation. */\r
\r
lw t0, 29 * portWORD_SIZE( sp ) /* mstatus */\r
csrrw x0, mstatus, t0 /* Interrupts enabled from here! */\r
projects / freertos / blobdiff