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<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/freedom-e-sdk/env}""/>\r
- <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/FreeRTOS_Source/portable/GCC/RISC-V-RV32/CLINT_no_extensions}""/>\r
+ <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/FreeRTOS_Source/portable/GCC/RISC-V-RV32}""/>\r
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/freedom-e-sdk/include}""/>\r
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/freedom-e-sdk/env/freedom-e300-hifive1}""/>\r
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/freedom-e-sdk/drivers}""/>\r
\r
<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.assembler.include.paths.1792818218" name="Include paths (-I)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.assembler.include.paths" useByScannerDiscovery="true" valueType="includePath">\r
\r
- <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/FreeRTOS_Source/portable/GCC/RISC-V-RV32/CLINT_no_extensions}""/>\r
+ <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/FreeRTOS_Source/portable/GCC/RISC-V-RV32}""/>\r
\r
</option>\r
\r
#endif\r
\r
.section .text.entry\r
- .extern vFreeRTOSPortTrapHandler\r
+ .extern freertos_risc_v_trap_handler\r
.globl _start\r
\r
_start:\r
j nmi_vector\r
\r
trap_vector:\r
- j vFreeRTOSPortTrapHandler\r
+ j freertos_risc_v_trap_handler\r
\r
handle_reset:\r
- la t0, vFreeRTOSPortTrapHandler\r
+ la t0, freertos_risc_v_trap_handler\r
csrw mtvec, t0\r
csrwi mstatus, 0\r
csrwi mie, 0\r
--- /dev/null
+/*\r
+ * FreeRTOS Kernel V10.1.1\r
+ * Copyright (C) 2018 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and t\r
+\r
+ o permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
+\r
+/*\r
+ * The FreeRTOS kernel's RISC-V port is split between the the code that is\r
+ * common across all currently supported RISC-V chips (implementations of the\r
+ * RISC-V ISA), and code which tailors the port to a specific RISC-V chip:\r
+ *\r
+ * + FreeRTOS\Source\portable\GCC\RISC-V-RV32\portASM.S contains the code that\r
+ * is common to all currently supported RISC-V chips. There is only one\r
+ * portASM.S file because the same file is built for all RISC-V target chips.\r
+ *\r
+ * + Header files called freertos_risc_v_chip_specific_extensions.h contain the\r
+ * code that tailors the FreeRTOS kernel's RISC-V port to a specific RISC-V\r
+ * chip. There are multiple freertos_risc_v_chip_specific_extensions.h files\r
+ * as there are multiple RISC-V chip implementations.\r
+ *\r
+ * !!!NOTE!!!\r
+ * CARE MUST BE TAKEN TO INCLUDE THE CORRECT\r
+ * freertos_risc_v_chip_specific_extensions.h HEADER FILE FOR THE CHIP IN USE.\r
+ * If the chip in use includes a core local interrupter (CLINT) and does not\r
+ * include any chip specific register extensions then set the GNU assembler's\r
+ * include path such that the header file contained in the\r
+ * FreeRTOS\Source\portable\GCC\RISC-V-RV32 directory is the header file that is\r
+ * actually inlcuded. Otherwise set the assembler's include patch to the\r
+ * sub-directory off of the\r
+ * FreeRTOS\Source\portable\GCC\RISC-V-RV32\chip_specific_extensions directory\r
+ * that contains the freertos_risc_v_chip_specific_extensions.h specific to the\r
+ * target chip.\r
+ *\r
+ */\r
+\r
+/*\r
+ * This freertos_risc_v_chip_specific_extensions.h is for use with Pulpino Ri5cy\r
+ * devices, developed and tested using the Vega board RV32M1RM.\r
+ */\r
+\r
+#ifndef __FREERTOS_RISC_V_EXTENSIONS_H__\r
+#define __FREERTOS_RISC_V_EXTENSIONS_H__\r
+\r
+#define portasmHAS_CLINT 0\r
+\r
+/* Constants to define the additional registers found on the Pulpino RI5KY. */\r
+#define lpstart0 0x7b0\r
+#define lpend0 0x7b1\r
+#define lpcount0 0x7b2\r
+#define lpstart1 0x7b4\r
+#define lpend1 0x7b5\r
+#define lpcount1 0x7b6\r
+\r
+/* Six additional registers to save and restore, as per the #defines above. */\r
+#define portasmADDITIONAL_CONTEXT_SIZE 6 /* Must be even number on 32-bit cores. */\r
+\r
+/* Save additional registers found on the Pulpino. */\r
+.macro portasmSAVE_ADDITIONAL_REGISTERS\r
+ addi sp, sp, -(portasmADDITIONAL_CONTEXT_SIZE * portWORD_SIZE) /* Make room for the additional registers. */\r
+ csrr t0, lpstart0 /* Load additional registers into accessable temporary registers. */\r
+ csrr t1, lpend0\r
+ csrr t2, lpcount0\r
+ csrr t3, lpstart1\r
+ csrr t4, lpend1\r
+ csrr t5, lpcount1\r
+ sw t0, 1 * portWORD_SIZE( sp )\r
+ sw t1, 2 * portWORD_SIZE( sp )\r
+ sw t2, 3 * portWORD_SIZE( sp )\r
+ sw t3, 4 * portWORD_SIZE( sp )\r
+ sw t4, 5 * portWORD_SIZE( sp )\r
+ sw t5, 6 * portWORD_SIZE( sp )\r
+ .endm\r
+\r
+/* Restore the additional registers found on the Pulpino. */\r
+.macro portasmRESTORE_ADDITIONAL_REGISTERS\r
+ lw t0, 1 * portWORD_SIZE( sp ) /* Load additional registers into accessable temporary registers. */\r
+ lw t1, 2 * portWORD_SIZE( sp )\r
+ lw t2, 3 * portWORD_SIZE( sp )\r
+ lw t3, 4 * portWORD_SIZE( sp )\r
+ lw t4, 5 * portWORD_SIZE( sp )\r
+ lw t5, 6 * portWORD_SIZE( sp )\r
+ csrw lpstart0, t0\r
+ csrw lpend0, t1\r
+ csrw lpcount0, t2\r
+ csrw lpstart1, t3\r
+ csrw lpend1, t4\r
+ csrw lpcount1, t5\r
+ addi sp, sp, (portasmADDITIONAL_CONTEXT_SIZE * portWORD_SIZE )/* Remove space added for additional registers. */\r
+ .endm\r
+\r
+#endif /* __FREERTOS_RISC_V_EXTENSIONS_H__ */\r
+++ /dev/null
-/*\r
- * FreeRTOS Kernel V10.1.1\r
- * Copyright (C) 2018 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
- *\r
- * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
- * this software and associated documentation files (the "Software"), to deal in\r
- * the Software without restriction, including without limitation the rights to\r
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
- * the Software, and t\r
-\r
- o permit persons to whom the Software is furnished to do so,\r
- * subject to the following conditions:\r
- *\r
- * The above copyright notice and this permission notice shall be included in all\r
- * copies or substantial portions of the Software.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
- *\r
- * http://www.FreeRTOS.org\r
- * http://aws.amazon.com/freertos\r
- *\r
- * 1 tab == 4 spaces!\r
- */\r
-\r
-/*\r
- * The FreeRTOS kernel's RISC-V port is split between the the code that is\r
- * common across all currently supported RISC-V chips (implementations of the\r
- * RISC-V ISA), and code which tailors the port to a specific RISC-V chip:\r
- *\r
- * + The code that is common to all RISC-V chips is implemented in\r
- * FreeRTOS\Source\portable\GCC\RISC-V-RV32\portASM.S. There is only one\r
- * portASM.S file because the same file is used no matter which RISC-V chip is\r
- * in use.\r
- *\r
- * + The code that tailors the kernel's RISC-V port to a specific RISC-V\r
- * chip is implemented in freertos_risc_v_port_specific_extensions.h. There\r
- * is one freertos_risc_v_port_specific_extensions.h that can be used with any\r
- * RISC-V chip that both includes a standard CLINT and does not add to the\r
- * base set of RISC-V registers. There are additional\r
- * freertos_risc_v_port_specific_extensions.h files for RISC-V implementations\r
- * that do not include a standard CLINT or do add to the base set of RISC-V\r
- * registers.\r
- *\r
- * CARE MUST BE TAKEN TO INCLDUE THE CORRECT\r
- * freertos_risc_v_port_specific_extensions.h HEADER FILE FOR THE CHIP\r
- * IN USE. To include the correct freertos_risc_v_port_specific_extensions.h\r
- * header file ensure the path to the correct header file is in the assembler's\r
- * include path.\r
- *\r
- * This freertos_risc_v_port_specific_extensions.h is for use with Pulpino Ri5cy\r
- * devices, developed and tested using the Vega board RV32M1RM.\r
- *\r
- */\r
-\r
-#ifndef __FREERTOS_RISC_V_EXTENSIONS_H__\r
-#define __FREERTOS_RISC_V_EXTENSIONS_H__\r
-\r
-#define portasmHAS_CLINT 0\r
-\r
-/* Constants to define the additional registers found on the Pulpino RI5KY. */\r
-#define lpstart0 0x7b0\r
-#define lpend0 0x7b1\r
-#define lpcount0 0x7b2\r
-#define lpstart1 0x7b4\r
-#define lpend1 0x7b5\r
-#define lpcount1 0x7b6\r
-\r
-/* Six additional registers to save and restore, as per the #defines above. */\r
-#define portasmADDITIONAL_CONTEXT_SIZE 6 /* Must be even number on 32-bit cores. */\r
-\r
-/* Save additional registers found on the Pulpino. */\r
-.macro portasmSAVE_ADDITIONAL_REGISTERS\r
- addi sp, sp, -(portasmADDITIONAL_CONTEXT_SIZE * portWORD_SIZE) /* Make room for the additional registers. */\r
- csrr t0, lpstart0 /* Load additional registers into accessable temporary registers. */\r
- csrr t1, lpend0\r
- csrr t2, lpcount0\r
- csrr t3, lpstart1\r
- csrr t4, lpend1\r
- csrr t5, lpcount1\r
- sw t0, 1 * portWORD_SIZE( sp )\r
- sw t1, 2 * portWORD_SIZE( sp )\r
- sw t2, 3 * portWORD_SIZE( sp )\r
- sw t3, 4 * portWORD_SIZE( sp )\r
- sw t4, 5 * portWORD_SIZE( sp )\r
- sw t5, 6 * portWORD_SIZE( sp )\r
- .endm\r
-\r
-/* Restore the additional registers found on the Pulpino. */\r
-.macro portasmRESTORE_ADDITIONAL_REGISTERS\r
- lw t0, 1 * portWORD_SIZE( sp ) /* Load additional registers into accessable temporary registers. */\r
- lw t1, 2 * portWORD_SIZE( sp )\r
- lw t2, 3 * portWORD_SIZE( sp )\r
- lw t3, 4 * portWORD_SIZE( sp )\r
- lw t4, 5 * portWORD_SIZE( sp )\r
- lw t5, 6 * portWORD_SIZE( sp )\r
- csrw lpstart0, t0\r
- csrw lpend0, t1\r
- csrw lpcount0, t2\r
- csrw lpstart1, t3\r
- csrw lpend1, t4\r
- csrw lpcount1, t5\r
- addi sp, sp, (portasmADDITIONAL_CONTEXT_SIZE * portWORD_SIZE )/* Remove space added for additional registers. */\r
- .endm\r
-\r
-#endif /* __FREERTOS_RISC_V_EXTENSIONS_H__ */\r
--- /dev/null
+/*\r
+ * The FreeRTOS kernel's RISC-V port is split between the the code that is\r
+ * common across all currently supported RISC-V chips (implementations of the\r
+ * RISC-V ISA), and code which tailors the port to a specific RISC-V chip:\r
+ *\r
+ * + FreeRTOS\Source\portable\GCC\RISC-V-RV32\portASM.S contains the code that\r
+ * is common to all currently supported RISC-V chips. There is only one\r
+ * portASM.S file because the same file is built for all RISC-V target chips.\r
+ *\r
+ * + Header files called freertos_risc_v_chip_specific_extensions.h contain the\r
+ * code that tailors the FreeRTOS kernel's RISC-V port to a specific RISC-V\r
+ * chip. There are multiple freertos_risc_v_chip_specific_extensions.h files\r
+ * as there are multiple RISC-V chip implementations.\r
+ *\r
+ * !!!NOTE!!!\r
+ * CARE MUST BE TAKEN TO INCLUDE THE CORRECT\r
+ * freertos_risc_v_chip_specific_extensions.h HEADER FILE FOR THE CHIP IN USE.\r
+ * If the chip in use includes a core local interrupter (CLINT) and does not\r
+ * include any chip specific register extensions then set the GNU assembler's\r
+ * include path such that the header file contained in the\r
+ * FreeRTOS\Source\portable\GCC\RISC-V-RV32 directory is the header file that is\r
+ * actually inlcuded. Otherwise set the assembler's include patch to the\r
+ * sub-directory off of the\r
+ * FreeRTOS\Source\portable\GCC\RISC-V-RV32\chip_specific_extensions directory\r
+ * that contains the freertos_risc_v_chip_specific_extensions.h specific to the\r
+ * target chip.\r
+ *\r
+ */\r
--- /dev/null
+/*\r
+ * FreeRTOS Kernel V10.1.1\r
+ * Copyright (C) 2018 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
+\r
+/*\r
+ * The FreeRTOS kernel's RISC-V port is split between the the code that is\r
+ * common across all currently supported RISC-V chips (implementations of the\r
+ * RISC-V ISA), and code which tailors the port to a specific RISC-V chip:\r
+ *\r
+ * + FreeRTOS\Source\portable\GCC\RISC-V-RV32\portASM.S contains the code that\r
+ * is common to all currently supported RISC-V chips. There is only one\r
+ * portASM.S file because the same file is built for all RISC-V target chips.\r
+ *\r
+ * + Header files called freertos_risc_v_chip_specific_extensions.h contain the\r
+ * code that tailors the FreeRTOS kernel's RISC-V port to a specific RISC-V\r
+ * chip. There are multiple freertos_risc_v_chip_specific_extensions.h files\r
+ * as there are multiple RISC-V chip implementations.\r
+ *\r
+ * !!!NOTE!!!\r
+ * CARE MUST BE TAKEN TO INCLUDE THE CORRECT\r
+ * freertos_risc_v_chip_specific_extensions.h HEADER FILE FOR THE CHIP IN USE.\r
+ * If the chip in use includes a core local interrupter (CLINT) and does not\r
+ * include any chip specific register extensions then set the GNU assembler's\r
+ * include path such that the header file contained in the\r
+ * FreeRTOS\Source\portable\GCC\RISC-V-RV32 directory is the header file that is\r
+ * actually inlcuded. Otherwise set the assembler's include patch to the\r
+ * sub-directory off of the\r
+ * FreeRTOS\Source\portable\GCC\RISC-V-RV32\chip_specific_extensions directory\r
+ * that contains the freertos_risc_v_chip_specific_extensions.h specific to the\r
+ * target chip.\r
+ *\r
+ */\r
+\r
+#ifndef __FREERTOS_RISC_V_EXTENSIONS_H__\r
+#define __FREERTOS_RISC_V_EXTENSIONS_H__\r
+\r
+#define portasmHAS_CLINT 1\r
+#define portasmADDITIONAL_CONTEXT_SIZE 0 /* Must be even number on 32-bit cores. */\r
+\r
+.macro portasmSAVE_ADDITIONAL_REGISTERS\r
+ /* No additional registers to save, so this macro does nothing. */\r
+ .endm\r
+\r
+/* Restore the additional registers found on the Pulpino. */\r
+.macro portasmRESTORE_ADDITIONAL_REGISTERS\r
+ /* No additional registers to restore, so this macro does nothing. */\r
+ .endm\r
+\r
+#endif /* __FREERTOS_RISC_V_EXTENSIONS_H__ */\r
+++ /dev/null
-/*\r
- * FreeRTOS Kernel V10.1.1\r
- * Copyright (C) 2018 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
- *\r
- * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
- * this software and associated documentation files (the "Software"), to deal in\r
- * the Software without restriction, including without limitation the rights to\r
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
- * the Software, and t\r
-\r
- o permit persons to whom the Software is furnished to do so,\r
- * subject to the following conditions:\r
- *\r
- * The above copyright notice and this permission notice shall be included in all\r
- * copies or substantial portions of the Software.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
- *\r
- * http://www.FreeRTOS.org\r
- * http://aws.amazon.com/freertos\r
- *\r
- * 1 tab == 4 spaces!\r
- */\r
-\r
-/*\r
- * The FreeRTOS kernel's RISC-V port is split between the the code that is\r
- * common across all currently supported RISC-V chips (implementations of the\r
- * RISC-V ISA), and code which tailors the port to a specific RISC-V chip:\r
- *\r
- * + The code that is common to all RISC-V chips is implemented in\r
- * FreeRTOS\Source\portable\GCC\RISC-V-RV32\portASM.S. There is only one\r
- * portASM.S file because the same file is used no matter which RISC-V chip is\r
- * in use.\r
- *\r
- * + The code that tailors the kernel's RISC-V port to a specific RISC-V\r
- * chip is implemented in freertos_risc_v_port_specific_extensions.h. There\r
- * is one freertos_risc_v_port_specific_extensions.h that can be used with any\r
- * RISC-V chip that both includes a standard CLINT and does not add to the\r
- * base set of RISC-V registers. There are additional\r
- * freertos_risc_v_port_specific_extensions.h files for RISC-V implementations\r
- * that do not include a standard CLINT or do add to the base set of RISC-V\r
- * registers.\r
- *\r
- * CARE MUST BE TAKEN TO INCLDUE THE CORRECT\r
- * freertos_risc_v_port_specific_extensions.h HEADER FILE FOR THE CHIP\r
- * IN USE. To include the correct freertos_risc_v_port_specific_extensions.h\r
- * header file ensure the path to the correct header file is in the assembler's\r
- * include path.\r
- *\r
- * This freertos_risc_v_port_specific_extensions.h is for use on RISC-V chips\r
- * that include a standard CLINT and do not add to the base set of RISC-V\r
- * registers.\r
- *\r
- */\r
-\r
-#ifndef __FREERTOS_RISC_V_EXTENSIONS_H__\r
-#define __FREERTOS_RISC_V_EXTENSIONS_H__\r
-\r
-#define portasmHAS_CLINT 1\r
-#define portasmADDITIONAL_CONTEXT_SIZE 0 /* Must be even number on 32-bit cores. */\r
-\r
-.macro portasmSAVE_ADDITIONAL_REGISTERS\r
- /* No additional registers to save, so this macro does nothing. */\r
- .endm\r
-\r
-/* Restore the additional registers found on the Pulpino. */\r
-.macro portasmRESTORE_ADDITIONAL_REGISTERS\r
- /* No additional registers to restore, so this macro does nothing. */\r
- .endm\r
-\r
-#endif /* __FREERTOS_RISC_V_EXTENSIONS_H__ */\r
* in use.\r
*\r
* + The code that tailors the kernel's RISC-V port to a specific RISC-V\r
- * chip is implemented in freertos_risc_v_port_specific_extensions.h. There\r
- * is one freertos_risc_v_port_specific_extensions.h that can be used with any\r
+ * chip is implemented in freertos_risc_v_chip_specific_extensions.h. There\r
+ * is one freertos_risc_v_chip_specific_extensions.h that can be used with any\r
* RISC-V chip that both includes a standard CLINT and does not add to the\r
* base set of RISC-V registers. There are additional\r
- * freertos_risc_v_port_specific_extensions.h files for RISC-V implementations\r
+ * freertos_risc_v_chip_specific_extensions.h files for RISC-V implementations\r
* that do not include a standard CLINT or do add to the base set of RISC-V\r
* registers.\r
*\r
* CARE MUST BE TAKEN TO INCLDUE THE CORRECT\r
- * freertos_risc_v_port_specific_extensions.h HEADER FILE FOR THE CHIP\r
- * IN USE. To include the correct freertos_risc_v_port_specific_extensions.h\r
+ * freertos_risc_v_chip_specific_extensions.h HEADER FILE FOR THE CHIP\r
+ * IN USE. To include the correct freertos_risc_v_chip_specific_extensions.h\r
* header file ensure the path to the correct header file is in the assembler's\r
* include path.\r
*\r
- * This freertos_risc_v_port_specific_extensions.h is for use on RISC-V chips\r
+ * This freertos_risc_v_chip_specific_extensions.h is for use on RISC-V chips\r
* that include a standard CLINT and do not add to the base set of RISC-V\r
* registers.\r
*\r
*/\r
-#include "freertos_risc_v_port_specific_extensions.h"\r
+#include "freertos_risc_v_chip_specific_extensions.h"\r
\r
-/* Check the freertos_risc_v_port_specific_extensions.h and/or command line\r
+/* Check the freertos_risc_v_chip_specific_extensions.h and/or command line\r
definitions. */\r
#ifndef portasmHAS_CLINT\r
- #error freertos_risc_v_port_specific_extensions.h must define portasmHAS_CLINT to either 1 (CLINT present) or 0 (clint not present).\r
+ #error freertos_risc_v_chip_specific_extensions.h must define portasmHAS_CLINT to either 1 (CLINT present) or 0 (clint not present).\r
#endif\r
\r
#ifndef portasmHANDLE_INTERRUPT\r
- #error portasmHANDLE_INTERRUPT must be defined to the function to be called to handle external/peripheral interrupts. portasmHANDLE_INTERRUPT can be defined on the assmbler command line or in the appropriate freertos_risc_v_port_specific_extensions.h header file.\r
+ #error portasmHANDLE_INTERRUPT must be defined to the function to be called to handle external/peripheral interrupts. portasmHANDLE_INTERRUPT can be defined on the assmbler command line or in the appropriate freertos_risc_v_chip_specific_extensions.h header file.\r
#endif\r
\r
/* Only the standard core registers are stored by default. Any additional\r
registers must be saved by the portasmSAVE_ADDITIONAL_REGISTERS and\r
portasmRESTORE_ADDITIONAL_REGISTERS macros - which can be defined in a chip\r
-specific version of freertos_risc_v_port_specific_extensions.h. See the notes\r
+specific version of freertos_risc_v_chip_specific_extensions.h. See the notes\r
at the top of this file. */\r
#define portCONTEXT_SIZE ( 30 * portWORD_SIZE )\r
\r
.global xPortStartFirstTask\r
-.global vFreeRTOSPortTrapHandler\r
+.global freertos_risc_v_trap_handler\r
.global pxPortInitialiseStack\r
.extern pxCurrentTCB\r
.extern ulPortTrapHandler\r
\r
.align 8\r
.func\r
-vFreeRTOSPortTrapHandler:\r
+freertos_risc_v_trap_handler:\r
addi sp, sp, -portCONTEXT_SIZE\r
sw x1, 1 * portWORD_SIZE( sp )\r
sw x5, 2 * portWORD_SIZE( sp )\r
csrr t0, mstatus /* Required for MPIE bit. */\r
sw t0, 29 * portWORD_SIZE( sp )\r
\r
- portasmSAVE_ADDITIONAL_REGISTERS /* Defined in freertos_risc_v_port_specific_extensions.h to save any registers unique to the RISC-V implementation. */\r
+ portasmSAVE_ADDITIONAL_REGISTERS /* Defined in freertos_risc_v_chip_specific_extensions.h to save any registers unique to the RISC-V implementation. */\r
\r
lw t0, pxCurrentTCB /* Load pxCurrentTCB. */\r
sw sp, 0( t0 ) /* Write sp to first TCB member. */\r
lw t0, 0( sp )\r
csrw mepc, t0\r
\r
- portasmRESTORE_ADDITIONAL_REGISTERS /* Defined in freertos_risc_v_port_specific_extensions.h to restore any registers unique to the RISC-V implementation. */\r
+ portasmRESTORE_ADDITIONAL_REGISTERS /* Defined in freertos_risc_v_chip_specific_extensions.h to restore any registers unique to the RISC-V implementation. */\r
\r
/* Load mstatus with the interrupt enable bits used by the task. */\r
lw t0, 29 * portWORD_SIZE( sp )\r
/* If there is a clint then interrupts can branch directly to the FreeRTOS\r
trap handler. Otherwise the interrupt controller will need to be configured\r
outside of this file. */\r
- la t0, vFreeRTOSPortTrapHandler\r
+ la t0, freertos_risc_v_trap_handler\r
csrw mtvec, t0\r
#endif /* portasmHAS_CLILNT */\r
\r
\r
lw x1, 0( sp ) /* Note for starting the scheduler the exception return address is used as the function return address. */\r
\r
- portasmRESTORE_ADDITIONAL_REGISTERS /* Defined in freertos_risc_v_port_specific_extensions.h to restore any registers unique to the RISC-V implementation. */\r
+ portasmRESTORE_ADDITIONAL_REGISTERS /* Defined in freertos_risc_v_chip_specific_extensions.h to restore any registers unique to the RISC-V implementation. */\r
\r
lw t0, 29 * portWORD_SIZE( sp ) /* mstatus */\r
csrrw x0, mstatus, t0 /* Interrupts enabled from here! */\r
+/*\r
* The FreeRTOS kernel's RISC-V port is split between the the code that is\r
* common across all currently supported RISC-V chips (implementations of the\r
* RISC-V ISA), and code which tailors the port to a specific RISC-V chip:\r
*\r
- * + The code that is common to all RISC-V chips is implemented in\r
- * FreeRTOS\Source\portable\GCC\RISC-V-RV32\portASM.S. There is only one\r
- * portASM.S file because the same file is used no matter which RISC-V chip is\r
- * in use.\r
+ * + FreeRTOS\Source\portable\GCC\RISC-V-RV32\portASM.S contains the code that\r
+ * is common to all currently supported RISC-V chips. There is only one\r
+ * portASM.S file because the same file is built for all RISC-V target chips.\r
*\r
- * + The code that tailors the kernel's RISC-V port to a specific RISC-V\r
- * chip is implemented in freertos_risc_v_port_specific_extensions.h. There\r
- * is one freertos_risc_v_port_specific_extensions.h that can be used with any\r
- * RISC-V chip that both includes a standard CLINT and does not add to the\r
- * base set of RISC-V registers. There are additional\r
- * freertos_risc_v_port_specific_extensions.h files for RISC-V implementations\r
- * that do not include a standard CLINT or do add to the base set of RISC-V\r
- * registers.\r
+ * + Header files called freertos_risc_v_chip_specific_extensions.h contain the\r
+ * code that tailors the FreeRTOS kernel's RISC-V port to a specific RISC-V\r
+ * chip. There are multiple freertos_risc_v_chip_specific_extensions.h files\r
+ * as there are multiple RISC-V chip implementations.\r
*\r
- * CARE MUST BE TAKEN TO INCLDUE THE CORRECT\r
- * freertos_risc_v_port_specific_extensions.h HEADER FILE FOR THE CHIP\r
- * IN USE. To include the correct freertos_risc_v_port_specific_extensions.h\r
- * header file ensure the path to the correct header file is in the assembler's\r
- * include path.\r
+ * !!!NOTE!!!\r
+ * CARE MUST BE TAKEN TO INCLUDE THE CORRECT\r
+ * freertos_risc_v_chip_specific_extensions.h HEADER FILE FOR THE CHIP IN USE.\r
+ * If the chip in use includes a core local interrupter (CLINT) and does not\r
+ * include any chip specific register extensions then set the GNU assembler's\r
+ * include path such that the header file contained in the\r
+ * FreeRTOS\Source\portable\GCC\RISC-V-RV32 directory is the header file that is\r
+ * actually inlcuded. Otherwise set the assembler's include patch to the\r
+ * sub-directory off of the\r
+ * FreeRTOS\Source\portable\GCC\RISC-V-RV32\chip_specific_extensions directory\r
+ * that contains the freertos_risc_v_chip_specific_extensions.h specific to the\r
+ * target chip.\r
*\r
- * This freertos_risc_v_port_specific_extensions.h is for use on RISC-V chips\r
- * that include a standard CLINT and do not add to the base set of RISC-V\r
- * registers.\r
+ */\r
projects / freertos / commitdiff