* 1 tab == 4 spaces!\r
*/\r
\r
- EXTERN pxCurrentTCB\r
- EXTERN xSecureContext\r
- EXTERN vTaskSwitchContext\r
- EXTERN vPortSVCHandler_C\r
- EXTERN SecureContext_SaveContext\r
- EXTERN SecureContext_LoadContext\r
+ EXTERN pxCurrentTCB\r
+ EXTERN xSecureContext\r
+ EXTERN vTaskSwitchContext\r
+ EXTERN vPortSVCHandler_C\r
+ EXTERN SecureContext_SaveContext\r
+ EXTERN SecureContext_LoadContext\r
\r
- PUBLIC xIsPrivileged\r
- PUBLIC vResetPrivilege\r
- PUBLIC vPortAllocateSecureContext\r
- PUBLIC vRestoreContextOfFirstTask\r
- PUBLIC vRaisePrivilege\r
- PUBLIC vStartFirstTask\r
- PUBLIC ulSetInterruptMaskFromISR\r
- PUBLIC vClearInterruptMaskFromISR\r
- PUBLIC PendSV_Handler\r
- PUBLIC SVC_Handler\r
- PUBLIC vPortFreeSecureContext\r
+ PUBLIC xIsPrivileged\r
+ PUBLIC vResetPrivilege\r
+ PUBLIC vPortAllocateSecureContext\r
+ PUBLIC vRestoreContextOfFirstTask\r
+ PUBLIC vRaisePrivilege\r
+ PUBLIC vStartFirstTask\r
+ PUBLIC ulSetInterruptMaskFromISR\r
+ PUBLIC vClearInterruptMaskFromISR\r
+ PUBLIC PendSV_Handler\r
+ PUBLIC SVC_Handler\r
+ PUBLIC vPortFreeSecureContext\r
/*-----------------------------------------------------------*/\r
\r
/*---------------- Unprivileged Functions -------------------*/\r
\r
/*-----------------------------------------------------------*/\r
\r
- SECTION .text:CODE:NOROOT(2)\r
- THUMB\r
+ SECTION .text:CODE:NOROOT(2)\r
+ THUMB\r
/*-----------------------------------------------------------*/\r
\r
xIsPrivileged:\r
- mrs r0, control /* r0 = CONTROL. */\r
- tst r0, #1 /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */\r
- ite ne\r
- movne r0, #0 /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */\r
- moveq r0, #1 /* CONTROL[0]==0. Return true to indicate that the processor is not privileged. */\r
- bx lr /* Return. */\r
+ mrs r0, control /* r0 = CONTROL. */\r
+ tst r0, #1 /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */\r
+ ite ne\r
+ movne r0, #0 /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */\r
+ moveq r0, #1 /* CONTROL[0]==0. Return true to indicate that the processor is not privileged. */\r
+ bx lr /* Return. */\r
/*-----------------------------------------------------------*/\r
\r
vResetPrivilege:\r
- mrs r0, control /* r0 = CONTROL. */\r
- orr r0, r0, #1 /* r0 = r0 | 1. */\r
- msr control, r0 /* CONTROL = r0. */\r
- bx lr /* Return to the caller. */\r
+ mrs r0, control /* r0 = CONTROL. */\r
+ orr r0, r0, #1 /* r0 = r0 | 1. */\r
+ msr control, r0 /* CONTROL = r0. */\r
+ bx lr /* Return to the caller. */\r
/*-----------------------------------------------------------*/\r
\r
vPortAllocateSecureContext:\r
- svc 0 /* Secure context is allocated in the supervisor call. portSVC_ALLOCATE_SECURE_CONTEXT = 0. */\r
- bx lr /* Return. */\r
+ svc 0 /* Secure context is allocated in the supervisor call. portSVC_ALLOCATE_SECURE_CONTEXT = 0. */\r
+ bx lr /* Return. */\r
/*-----------------------------------------------------------*/\r
\r
/*----------------- Privileged Functions --------------------*/\r
\r
/*-----------------------------------------------------------*/\r
\r
- SECTION privileged_functions:CODE:NOROOT(2)\r
- THUMB\r
+ SECTION privileged_functions:CODE:NOROOT(2)\r
+ THUMB\r
/*-----------------------------------------------------------*/\r
\r
vRestoreContextOfFirstTask:\r
- ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
- ldr r3, [r2] /* Read pxCurrentTCB. */\r
- ldr r0, [r3] /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */\r
+ ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
+ ldr r3, [r2] /* Read pxCurrentTCB. */\r
+ ldr r0, [r3] /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */\r
\r
#if ( configENABLE_MPU == 1 )\r
- adds r3, #4 /* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */\r
- ldr r4, [r3] /* r4 = *r3 i.e. r4 = MAIR0. */\r
- ldr r2, =0xe000edc0 /* r2 = 0xe000edc0 [Location of MAIR0]. */\r
- str r4, [r2] /* Program MAIR0. */\r
- ldr r2, =0xe000ed98 /* r2 = 0xe000ed98 [Location of RNR]. */\r
- movs r4, #4 /* r4 = 4. */\r
- str r4, [r2] /* Program RNR = 4. */\r
- adds r3, #4 /* r3 = r3 + 4. r3 now points to first RBAR in TCB. */\r
- ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */\r
- ldmia r3!, {r4-r11} /* Read 4 set of RBAR/RLAR registers from TCB. */\r
- stmia r2!, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */\r
+ adds r3, #4 /* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */\r
+ ldr r4, [r3] /* r4 = *r3 i.e. r4 = MAIR0. */\r
+ ldr r2, =0xe000edc0 /* r2 = 0xe000edc0 [Location of MAIR0]. */\r
+ str r4, [r2] /* Program MAIR0. */\r
+ ldr r2, =0xe000ed98 /* r2 = 0xe000ed98 [Location of RNR]. */\r
+ movs r4, #4 /* r4 = 4. */\r
+ str r4, [r2] /* Program RNR = 4. */\r
+ adds r3, #4 /* r3 = r3 + 4. r3 now points to first RBAR in TCB. */\r
+ ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */\r
+ ldmia r3!, {r4-r11} /* Read 4 set of RBAR/RLAR registers from TCB. */\r
+ stmia r2!, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */\r
#endif /* configENABLE_MPU */\r
\r
#if ( configENABLE_MPU == 1 )\r
- ldm r0!, {r1-r4} /* Read from stack - r1 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = EXC_RETURN. */\r
- ldr r5, =xSecureContext\r
- str r1, [r5] /* Set xSecureContext to this task's value for the same. */\r
- msr psplim, r2 /* Set this task's PSPLIM value. */\r
- msr control, r3 /* Set this task's CONTROL value. */\r
- adds r0, #32 /* Discard everything up to r0. */\r
- msr psp, r0 /* This is now the new top of stack to use in the task. */\r
- isb\r
- bx r4 /* Finally, branch to EXC_RETURN. */\r
+ ldm r0!, {r1-r4} /* Read from stack - r1 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = EXC_RETURN. */\r
+ ldr r5, =xSecureContext\r
+ str r1, [r5] /* Set xSecureContext to this task's value for the same. */\r
+ msr psplim, r2 /* Set this task's PSPLIM value. */\r
+ msr control, r3 /* Set this task's CONTROL value. */\r
+ adds r0, #32 /* Discard everything up to r0. */\r
+ msr psp, r0 /* This is now the new top of stack to use in the task. */\r
+ isb\r
+ bx r4 /* Finally, branch to EXC_RETURN. */\r
#else /* configENABLE_MPU */\r
- ldm r0!, {r1-r3} /* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */\r
- ldr r4, =xSecureContext\r
- str r1, [r4] /* Set xSecureContext to this task's value for the same. */\r
- msr psplim, r2 /* Set this task's PSPLIM value. */\r
- movs r1, #2 /* r1 = 2. */\r
- msr CONTROL, r1 /* Switch to use PSP in the thread mode. */\r
- adds r0, #32 /* Discard everything up to r0. */\r
- msr psp, r0 /* This is now the new top of stack to use in the task. */\r
- isb\r
- bx r3 /* Finally, branch to EXC_RETURN. */\r
+ ldm r0!, {r1-r3} /* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */\r
+ ldr r4, =xSecureContext\r
+ str r1, [r4] /* Set xSecureContext to this task's value for the same. */\r
+ msr psplim, r2 /* Set this task's PSPLIM value. */\r
+ movs r1, #2 /* r1 = 2. */\r
+ msr CONTROL, r1 /* Switch to use PSP in the thread mode. */\r
+ adds r0, #32 /* Discard everything up to r0. */\r
+ msr psp, r0 /* This is now the new top of stack to use in the task. */\r
+ isb\r
+ bx r3 /* Finally, branch to EXC_RETURN. */\r
#endif /* configENABLE_MPU */\r
/*-----------------------------------------------------------*/\r
\r
vRaisePrivilege:\r
- mrs r0, control /* Read the CONTROL register. */\r
- bic r0, r0, #1 /* Clear the bit 0. */\r
- msr control, r0 /* Write back the new CONTROL value. */\r
- bx lr /* Return to the caller. */\r
+ mrs r0, control /* Read the CONTROL register. */\r
+ bic r0, r0, #1 /* Clear the bit 0. */\r
+ msr control, r0 /* Write back the new CONTROL value. */\r
+ bx lr /* Return to the caller. */\r
/*-----------------------------------------------------------*/\r
\r
vStartFirstTask:\r
- ldr r0, =0xe000ed08 /* Use the NVIC offset register to locate the stack. */\r
- ldr r0, [r0] /* Read the VTOR register which gives the address of vector table. */\r
- ldr r0, [r0] /* The first entry in vector table is stack pointer. */\r
- msr msp, r0 /* Set the MSP back to the start of the stack. */\r
- cpsie i /* Globally enable interrupts. */\r
- cpsie f\r
- dsb\r
- isb\r
- svc 2 /* System call to start the first task. portSVC_START_SCHEDULER = 2. */\r
+ ldr r0, =0xe000ed08 /* Use the NVIC offset register to locate the stack. */\r
+ ldr r0, [r0] /* Read the VTOR register which gives the address of vector table. */\r
+ ldr r0, [r0] /* The first entry in vector table is stack pointer. */\r
+ msr msp, r0 /* Set the MSP back to the start of the stack. */\r
+ cpsie i /* Globally enable interrupts. */\r
+ cpsie f\r
+ dsb\r
+ isb\r
+ svc 2 /* System call to start the first task. portSVC_START_SCHEDULER = 2. */\r
/*-----------------------------------------------------------*/\r
\r
ulSetInterruptMaskFromISR:\r
- mrs r0, PRIMASK\r
- cpsid i\r
- bx lr\r
+ mrs r0, PRIMASK\r
+ cpsid i\r
+ bx lr\r
/*-----------------------------------------------------------*/\r
\r
vClearInterruptMaskFromISR:\r
- msr PRIMASK, r0\r
- bx lr\r
+ msr PRIMASK, r0\r
+ bx lr\r
/*-----------------------------------------------------------*/\r
\r
PendSV_Handler:\r
- mrs r1, psp /* Read PSP in r1. */\r
- ldr r2, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */\r
- ldr r0, [r2] /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */\r
+ mrs r1, psp /* Read PSP in r1. */\r
+ ldr r2, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */\r
+ ldr r0, [r2] /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */\r
\r
- cbz r0, save_ns_context /* No secure context to save. */\r
- push {r0-r2, r14}\r
- bl SecureContext_SaveContext\r
- pop {r0-r3} /* LR is now in r3. */\r
- mov lr, r3 /* LR = r3. */\r
- lsls r2, r3, #25 /* r2 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */\r
- bpl save_ns_context /* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */\r
- ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
- ldr r2, [r3] /* Read pxCurrentTCB. */\r
+ cbz r0, save_ns_context /* No secure context to save. */\r
+ push {r0-r2, r14}\r
+ bl SecureContext_SaveContext\r
+ pop {r0-r3} /* LR is now in r3. */\r
+ mov lr, r3 /* LR = r3. */\r
+ lsls r2, r3, #25 /* r2 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */\r
+ bpl save_ns_context /* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */\r
+ ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
+ ldr r2, [r3] /* Read pxCurrentTCB. */\r
#if ( configENABLE_MPU == 1 )\r
- subs r1, r1, #16 /* Make space for xSecureContext, PSPLIM, CONTROL and LR on the stack. */\r
- str r1, [r2] /* Save the new top of stack in TCB. */\r
- mrs r2, psplim /* r2 = PSPLIM. */\r
- mrs r3, control /* r3 = CONTROL. */\r
- mov r4, lr /* r4 = LR/EXC_RETURN. */\r
- stmia r1!, {r0, r2-r4} /* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */\r
+ subs r1, r1, #16 /* Make space for xSecureContext, PSPLIM, CONTROL and LR on the stack. */\r
+ str r1, [r2] /* Save the new top of stack in TCB. */\r
+ mrs r2, psplim /* r2 = PSPLIM. */\r
+ mrs r3, control /* r3 = CONTROL. */\r
+ mov r4, lr /* r4 = LR/EXC_RETURN. */\r
+ stmia r1!, {r0, r2-r4} /* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */\r
#else /* configENABLE_MPU */\r
- subs r1, r1, #12 /* Make space for xSecureContext, PSPLIM and LR on the stack. */\r
- str r1, [r2] /* Save the new top of stack in TCB. */\r
- mrs r2, psplim /* r2 = PSPLIM. */\r
- mov r3, lr /* r3 = LR/EXC_RETURN. */\r
- stmia r1!, {r0, r2-r3} /* Store xSecureContext, PSPLIM and LR on the stack. */\r
+ subs r1, r1, #12 /* Make space for xSecureContext, PSPLIM and LR on the stack. */\r
+ str r1, [r2] /* Save the new top of stack in TCB. */\r
+ mrs r2, psplim /* r2 = PSPLIM. */\r
+ mov r3, lr /* r3 = LR/EXC_RETURN. */\r
+ stmia r1!, {r0, r2-r3} /* Store xSecureContext, PSPLIM and LR on the stack. */\r
#endif /* configENABLE_MPU */\r
- b select_next_task\r
+ b select_next_task\r
\r
- save_ns_context:\r
- ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
- ldr r2, [r3] /* Read pxCurrentTCB. */\r
- #if ( configENABLE_FPU == 1 )\r
- tst lr, #0x10 /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */\r
- it eq\r
- vstmdbeq r1!, {s16-s31} /* Store the FPU registers which are not saved automatically. */\r
- #endif /* configENABLE_FPU */\r
- #if ( configENABLE_MPU == 1 )\r
- subs r1, r1, #48 /* Make space for xSecureContext, PSPLIM, CONTROL, LR and the remaining registers on the stack. */\r
- str r1, [r2] /* Save the new top of stack in TCB. */\r
- adds r1, r1, #16 /* r1 = r1 + 16. */\r
- stm r1, {r4-r11} /* Store the registers that are not saved automatically. */\r
- mrs r2, psplim /* r2 = PSPLIM. */\r
- mrs r3, control /* r3 = CONTROL. */\r
- mov r4, lr /* r4 = LR/EXC_RETURN. */\r
- subs r1, r1, #16 /* r1 = r1 - 16. */\r
- stm r1, {r0, r2-r4} /* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */\r
- #else /* configENABLE_MPU */\r
- subs r1, r1, #44 /* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */\r
- str r1, [r2] /* Save the new top of stack in TCB. */\r
- adds r1, r1, #12 /* r1 = r1 + 12. */\r
- stm r1, {r4-r11} /* Store the registers that are not saved automatically. */\r
- mrs r2, psplim /* r2 = PSPLIM. */\r
- mov r3, lr /* r3 = LR/EXC_RETURN. */\r
- subs r1, r1, #12 /* r1 = r1 - 12. */\r
- stmia r1!, {r0, r2-r3} /* Store xSecureContext, PSPLIM and LR on the stack. */\r
- #endif /* configENABLE_MPU */\r
+ save_ns_context:\r
+ ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
+ ldr r2, [r3] /* Read pxCurrentTCB. */\r
+ #if ( configENABLE_FPU == 1 )\r
+ tst lr, #0x10 /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */\r
+ it eq\r
+ vstmdbeq r1!, {s16-s31} /* Store the FPU registers which are not saved automatically. */\r
+ #endif /* configENABLE_FPU */\r
+ #if ( configENABLE_MPU == 1 )\r
+ subs r1, r1, #48 /* Make space for xSecureContext, PSPLIM, CONTROL, LR and the remaining registers on the stack. */\r
+ str r1, [r2] /* Save the new top of stack in TCB. */\r
+ adds r1, r1, #16 /* r1 = r1 + 16. */\r
+ stm r1, {r4-r11} /* Store the registers that are not saved automatically. */\r
+ mrs r2, psplim /* r2 = PSPLIM. */\r
+ mrs r3, control /* r3 = CONTROL. */\r
+ mov r4, lr /* r4 = LR/EXC_RETURN. */\r
+ subs r1, r1, #16 /* r1 = r1 - 16. */\r
+ stm r1, {r0, r2-r4} /* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */\r
+ #else /* configENABLE_MPU */\r
+ subs r1, r1, #44 /* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */\r
+ str r1, [r2] /* Save the new top of stack in TCB. */\r
+ adds r1, r1, #12 /* r1 = r1 + 12. */\r
+ stm r1, {r4-r11} /* Store the registers that are not saved automatically. */\r
+ mrs r2, psplim /* r2 = PSPLIM. */\r
+ mov r3, lr /* r3 = LR/EXC_RETURN. */\r
+ subs r1, r1, #12 /* r1 = r1 - 12. */\r
+ stmia r1!, {r0, r2-r3} /* Store xSecureContext, PSPLIM and LR on the stack. */\r
+ #endif /* configENABLE_MPU */\r
\r
- select_next_task:\r
- cpsid i\r
- bl vTaskSwitchContext\r
- cpsie i\r
+ select_next_task:\r
+ cpsid i\r
+ bl vTaskSwitchContext\r
+ cpsie i\r
\r
- ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
- ldr r3, [r2] /* Read pxCurrentTCB. */\r
- ldr r1, [r3] /* The first item in pxCurrentTCB is the task top of stack. r1 now points to the top of stack. */\r
+ ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
+ ldr r3, [r2] /* Read pxCurrentTCB. */\r
+ ldr r1, [r3] /* The first item in pxCurrentTCB is the task top of stack. r1 now points to the top of stack. */\r
\r
- #if ( configENABLE_MPU == 1 )\r
- adds r3, #4 /* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */\r
- ldr r4, [r3] /* r4 = *r3 i.e. r4 = MAIR0. */\r
- ldr r2, =0xe000edc0 /* r2 = 0xe000edc0 [Location of MAIR0]. */\r
- str r4, [r2] /* Program MAIR0. */\r
- ldr r2, =0xe000ed98 /* r2 = 0xe000ed98 [Location of RNR]. */\r
- movs r4, #4 /* r4 = 4. */\r
- str r4, [r2] /* Program RNR = 4. */\r
- adds r3, #4 /* r3 = r3 + 4. r3 now points to first RBAR in TCB. */\r
- ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */\r
- ldmia r3!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */\r
- stmia r2!, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */\r
- #endif /* configENABLE_MPU */\r
+ #if ( configENABLE_MPU == 1 )\r
+ adds r3, #4 /* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */\r
+ ldr r4, [r3] /* r4 = *r3 i.e. r4 = MAIR0. */\r
+ ldr r2, =0xe000edc0 /* r2 = 0xe000edc0 [Location of MAIR0]. */\r
+ str r4, [r2] /* Program MAIR0. */\r
+ ldr r2, =0xe000ed98 /* r2 = 0xe000ed98 [Location of RNR]. */\r
+ movs r4, #4 /* r4 = 4. */\r
+ str r4, [r2] /* Program RNR = 4. */\r
+ adds r3, #4 /* r3 = r3 + 4. r3 now points to first RBAR in TCB. */\r
+ ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */\r
+ ldmia r3!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */\r
+ stmia r2!, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */\r
+ #endif /* configENABLE_MPU */\r
\r
- #if ( configENABLE_MPU == 1 )\r
- ldmia r1!, {r0, r2-r4} /* Read from stack - r0 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = LR. */\r
- msr psplim, r2 /* Restore the PSPLIM register value for the task. */\r
- msr control, r3 /* Restore the CONTROL register value for the task. */\r
- mov lr, r4 /* LR = r4. */\r
- ldr r2, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */\r
- str r0, [r2] /* Restore the task's xSecureContext. */\r
- cbz r0, restore_ns_context /* If there is no secure context for the task, restore the non-secure context. */\r
- push {r1,r4}\r
- bl SecureContext_LoadContext /* Restore the secure context. */\r
- pop {r1,r4}\r
- mov lr, r4 /* LR = r4. */\r
- lsls r2, r4, #25 /* r2 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */\r
- bpl restore_ns_context /* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */\r
- msr psp, r1 /* Remember the new top of stack for the task. */\r
- bx lr\r
- #else /* configENABLE_MPU */\r
- ldmia r1!, {r0, r2-r3} /* Read from stack - r0 = xSecureContext, r2 = PSPLIM and r3 = LR. */\r
- msr psplim, r2 /* Restore the PSPLIM register value for the task. */\r
- mov lr, r3 /* LR = r3. */\r
- ldr r2, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */\r
- str r0, [r2] /* Restore the task's xSecureContext. */\r
- cbz r0, restore_ns_context /* If there is no secure context for the task, restore the non-secure context. */\r
- push {r1,r3}\r
- bl SecureContext_LoadContext /* Restore the secure context. */\r
- pop {r1,r3}\r
- mov lr, r3 /* LR = r3. */\r
- lsls r2, r3, #25 /* r2 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */\r
- bpl restore_ns_context /* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */\r
- msr psp, r1 /* Remember the new top of stack for the task. */\r
- bx lr\r
- #endif /* configENABLE_MPU */\r
+ #if ( configENABLE_MPU == 1 )\r
+ ldmia r1!, {r0, r2-r4} /* Read from stack - r0 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = LR. */\r
+ msr psplim, r2 /* Restore the PSPLIM register value for the task. */\r
+ msr control, r3 /* Restore the CONTROL register value for the task. */\r
+ mov lr, r4 /* LR = r4. */\r
+ ldr r2, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */\r
+ str r0, [r2] /* Restore the task's xSecureContext. */\r
+ cbz r0, restore_ns_context /* If there is no secure context for the task, restore the non-secure context. */\r
+ push {r1,r4}\r
+ bl SecureContext_LoadContext /* Restore the secure context. */\r
+ pop {r1,r4}\r
+ mov lr, r4 /* LR = r4. */\r
+ lsls r2, r4, #25 /* r2 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */\r
+ bpl restore_ns_context /* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */\r
+ msr psp, r1 /* Remember the new top of stack for the task. */\r
+ bx lr\r
+ #else /* configENABLE_MPU */\r
+ ldmia r1!, {r0, r2-r3} /* Read from stack - r0 = xSecureContext, r2 = PSPLIM and r3 = LR. */\r
+ msr psplim, r2 /* Restore the PSPLIM register value for the task. */\r
+ mov lr, r3 /* LR = r3. */\r
+ ldr r2, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */\r
+ str r0, [r2] /* Restore the task's xSecureContext. */\r
+ cbz r0, restore_ns_context /* If there is no secure context for the task, restore the non-secure context. */\r
+ push {r1,r3}\r
+ bl SecureContext_LoadContext /* Restore the secure context. */\r
+ pop {r1,r3}\r
+ mov lr, r3 /* LR = r3. */\r
+ lsls r2, r3, #25 /* r2 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */\r
+ bpl restore_ns_context /* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */\r
+ msr psp, r1 /* Remember the new top of stack for the task. */\r
+ bx lr\r
+ #endif /* configENABLE_MPU */\r
\r
- restore_ns_context:\r
- ldmia r1!, {r4-r11} /* Restore the registers that are not automatically restored. */\r
- #if ( configENABLE_FPU == 1 )\r
- tst lr, #0x10 /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */\r
- it eq\r
- vldmiaeq r1!, {s16-s31} /* Restore the FPU registers which are not restored automatically. */\r
- #endif /* configENABLE_FPU */\r
- msr psp, r1 /* Remember the new top of stack for the task. */\r
- bx lr\r
+ restore_ns_context:\r
+ ldmia r1!, {r4-r11} /* Restore the registers that are not automatically restored. */\r
+ #if ( configENABLE_FPU == 1 )\r
+ tst lr, #0x10 /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */\r
+ it eq\r
+ vldmiaeq r1!, {s16-s31} /* Restore the FPU registers which are not restored automatically. */\r
+ #endif /* configENABLE_FPU */\r
+ msr psp, r1 /* Remember the new top of stack for the task. */\r
+ bx lr\r
/*-----------------------------------------------------------*/\r
\r
SVC_Handler:\r
- tst lr, #4\r
- ite eq\r
- mrseq r0, msp\r
- mrsne r0, psp\r
- b vPortSVCHandler_C\r
+ tst lr, #4\r
+ ite eq\r
+ mrseq r0, msp\r
+ mrsne r0, psp\r
+ b vPortSVCHandler_C\r
/*-----------------------------------------------------------*/\r
\r
vPortFreeSecureContext:\r
- /* r0 = uint32_t *pulTCB. */\r
- ldr r1, [r0] /* The first item in the TCB is the top of the stack. */\r
- ldr r0, [r1] /* The first item on the stack is the task's xSecureContext. */\r
- cmp r0, #0 /* Raise svc if task's xSecureContext is not NULL. */\r
- it ne\r
- svcne 1 /* Secure context is freed in the supervisor call. portSVC_FREE_SECURE_CONTEXT = 1. */\r
- bx lr /* Return. */\r
+ /* r0 = uint32_t *pulTCB. */\r
+ ldr r1, [r0] /* The first item in the TCB is the top of the stack. */\r
+ ldr r0, [r1] /* The first item on the stack is the task's xSecureContext. */\r
+ cmp r0, #0 /* Raise svc if task's xSecureContext is not NULL. */\r
+ it ne\r
+ svcne 1 /* Secure context is freed in the supervisor call. portSVC_FREE_SECURE_CONTEXT = 1. */\r
+ bx lr /* Return. */\r
/*-----------------------------------------------------------*/\r
\r
- END\r
+ END\r
projects / freertos / blobdiff