ADIv5: cleanup, rename swjdp_transaction_endcheck()

[openocd] / NEWS

diff --git a/NEWS b/NEWS
index e3e813cbae5e9b3528f57d6fe9affec8e41ae856..f7bf1d313255b6e3ff55df8a0834e127f5138a62 100644 (file)
--- a/NEWS
+++ b/NEWS
@@ -8,34 +8,43 @@ JTAG Layer:
        Support USB-JTAG, Altera USB-Blaster and compatibles.
 
 Boundary Scan:
+
 Target Layer:
        General
                - new "reset-assert" event, for systems without SRST
        ARM
+               - supports "reset-assert" event (except on Cortex-M3)
                - renamed "armv4_5" command prefix as "arm"
                - recognize TrustZone "Secure Monitor" mode
                - "arm regs" command output changed
                - register names use "sp" not "r13"
                - add top-level "mcr" and "mrc" commands, replacing
                  various core-specific operations
-               - basic semihosting support
+               - basic semihosting support (ARM7/ARM9 only, for now)
        ARM11
-               - Preliminary ETM and ETB hookup
-               - accelerated "flash erase_check"
-               - accelerated GDB memory checksum
-               - support "arm regs" command
-               - can access all core modes and registers
-               - watchpoint support
+               - Should act much more like other ARM cores:
+                  * Preliminary ETM and ETB hookup
+                  * accelerated "flash erase_check"
+                  * accelerated GDB memory checksum
+                  * support "arm regs" command
+                  * can access all core modes and registers
+                  * watchpoint support
+               - Shares some core debug code with Cortex-A8
        Cortex-A8
-               - support "arm regs" command
-               - can access all core modes and registers
-               - supports "reset-assert" event (used on OMAP3530)
-               - watchpoint support
+               - Should act much more like other ARM cores:
+                  * support "arm regs" command
+                  * can access all core modes and registers
+                  * watchpoint support
+               - Shares some core debug code with ARM11
        Cortex-M3
                - Exposed DWT registers like cycle counter
+               - vector_catch settings not clobbered by resets
+               - no longer interferes with firmware's fault handling
        ETM, ETB
                - "trigger_percent" command moved ETM --> ETB
                - "etm trigger_debug" command added
+       MIPS
+               - use fastdata writes
        Freescale DSP563xx cores (partial support)
 
 Flash Layer:
@@ -45,13 +54,19 @@ Flash Layer:
                - <driver_name>[.N]: reference the driver's Nth bank
        New 'nand verify' command to check bank against an image file.
        The "flash erase_address" command now rejects partial sectors;
-               previously it would silently erase extra data.
+               previously it would silently erase extra data.  If you
+               want to erase the rest of the first and/or last sectors
+               instead of failing, you must pass an explicit "pad" flag.
        New at91sam9 NAND controller driver.
+       New s3c64xx NAND controller driver.
 
 Board, Target, and Interface Configuration Scripts:
        ARM9
                - ETM and ETB hookup for iMX2* targets
        Add $HOME/.openocd to the search path.
+       Handle Rev C of LM3S811 eval boards.
+               - use "luminary-lm3s811.cfg" for older boards
+               - use "luminary.cfg" for RevC and newer
 
 Core Jim/TCL Scripting:
        New 'usage' command to provide terse command help.
@@ -78,4 +93,4 @@ For older NEWS, see the NEWS files associated with each release
 
 For more information about contributing test reports, bug fixes, or new
 features and device support, please read the new Developer Manual (or
-the BUGS and PATCHES files in the source archive).
+the BUGS and PATCHES.txt files in the source archive).