Blackfin: adi boards: also set stderr to nc with helper

[u-boot] / README

diff --git a/README b/README
index 446966dc16f5dc353daed8ede6b4e26ea997dafa..1e2d4d33c0665972e0a881a9a10a53eccc63548f 100644 (file)
--- a/README
+++ b/README
@@ -460,6 +460,17 @@ The following options need to be configured:
                Note: If a "bootargs" environment is defined, it will overwride
                the defaults discussed just above.
 
+- Cache Configuration:
+               CONFIG_SYS_ICACHE_OFF - Do not enable instruction cache in U-Boot
+               CONFIG_SYS_DCACHE_OFF - Do not enable data cache in U-Boot
+               CONFIG_SYS_L2CACHE_OFF- Do not enable L2 cache in U-Boot
+
+- Cache Configuration for ARM:
+               CONFIG_SYS_L2_PL310 - Enable support for ARM PL310 L2 cache
+                                     controller
+               CONFIG_SYS_PL310_BASE - Physical base address of PL310
+                                       controller register space
+
 - Serial Ports:
                CONFIG_PL010_SERIAL
 
@@ -2917,6 +2928,14 @@ Low Level (hardware related) configuration options:
 - CONFIG_SYS_SRIOn_MEM_SIZE:
                Size of SRIO port 'n' memory region
 
+- CONFIG_SYS_NDFC_16
+               Defined to tell the NDFC that the NAND chip is using a
+               16 bit bus.
+
+- CONFIG_SYS_NDFC_EBC0_CFG
+               Sets the EBC0_CFG register for the NDFC. If not defined
+               a default value will be used.
+
 - CONFIG_SPD_EEPROM
                Get DDR timing information from an I2C EEPROM. Common
                with pluggable memory modules such as SODIMMs
@@ -2929,6 +2948,12 @@ Low Level (hardware related) configuration options:
                one, specify here. Note that the value must resolve
                to something your driver can deal with.
 
+- CONFIG_SYS_DDR_RAW_TIMING
+               Get DDR timing information from other than SPD. Common with
+               soldered DDR chips onboard without SPD. DDR raw timing
+               parameters are extracted from datasheet and hard-coded into
+               header files or board specific files.
+
 - CONFIG_SYS_83XX_DDR_USES_CS0
                Only for 83xx systems. If specified, then DDR should
                be configured using CS0 and CS1 instead of CS2 and CS3.