ICache only when Code runs from RAM.
- 85xx CPU Options:
+ CONFIG_SYS_PPC64
+
+ Specifies that the core is a 64-bit PowerPC implementation (implements
+ the "64" category of the Power ISA). This is necessary for ePAPR
+ compliance, among other possible reasons.
+
CONFIG_SYS_FSL_TBCLK_DIV
Defines the core time base clock divider ratio compared to the
CONFIG_CALXEDA_XGMAC
Support for the Calxeda XGMAC device
- CONFIG_DRIVER_LAN91C96
+ CONFIG_LAN91C96
Support for SMSC's LAN91C96 chips.
CONFIG_LAN91C96_BASE
CONFIG_LAN91C96_USE_32_BIT
Define this to enable 32 bit addressing
- CONFIG_DRIVER_SMC91111
+ CONFIG_SMC91111
Support for SMSC's LAN91C111 chip
CONFIG_SMC91111_BASE
following board configurations are known to be
"pRAM-clean":
- ETX094, IVMS8, IVML24, SPD8xx, TQM8xxL,
- HERMES, IP860, RPXlite, LWMON, LANTEC,
+ IVMS8, IVML24, SPD8xx, TQM8xxL,
+ HERMES, IP860, RPXlite, LWMON,
FLAGADM, TQM8260
- Error Recovery: