net: rtl8169: Add support for RTL-8168/8111g

[u-boot] / README

diff --git a/README b/README
index bfefa21b3bfd568bee43322e6210ff39dc151257..5af345b0860959c94451383b8389a833f83ec159 100644 (file)
--- a/README
+++ b/README
@@ -409,6 +409,10 @@ The following options need to be configured:
                Enables a workaround for IFC erratum A003399. It is only
                requred during NOR boot.
 
+               CONFIG_A008044_WORKAROUND
+               Enables a workaround for T1040/T1042 erratum A008044. It is only
+               requred during NAND boot and valid for Rev 1.0 SoC revision
+
                CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY
 
                This is the value to write into CCSR offset 0x18600
@@ -4003,6 +4007,25 @@ Configuration Settings:
                boards which do not use the full malloc in SPL (which is
                enabled with CONFIG_SYS_SPL_MALLOC_START).
 
+- CONFIG_SYS_NONCACHED_MEMORY:
+               Size of non-cached memory area. This area of memory will be
+               typically located right below the malloc() area and mapped
+               uncached in the MMU. This is useful for drivers that would
+               otherwise require a lot of explicit cache maintenance. For
+               some drivers it's also impossible to properly maintain the
+               cache. For example if the regions that need to be flushed
+               are not a multiple of the cache-line size, *and* padding
+               cannot be allocated between the regions to align them (i.e.
+               if the HW requires a contiguous array of regions, and the
+               size of each region is not cache-aligned), then a flush of
+               one region may result in overwriting data that hardware has
+               written to another region in the same cache-line. This can
+               happen for example in network drivers where descriptors for
+               buffers are typically smaller than the CPU cache-line (e.g.
+               16 bytes vs. 32 or 64 bytes).
+
+               Non-cached memory is only supported on 32-bit ARM at present.
+
 - CONFIG_SYS_BOOTM_LEN:
                Normally compressed uImages are limited to an
                uncompressed size of 8 MBytes. If this is not enough,