DaVinci EMAC: Fix davinci_eth_gigabit_enable

[u-boot] / README

diff --git a/README b/README
index 831c5af15c302e9cf63cf6bf2af3f4257c726503..755d17cc34b12d5209c4a182d652c0075403acc2 100644 (file)
--- a/README
+++ b/README
@@ -675,7 +675,7 @@ The following options need to be configured:
                                          (requires CONFIG_CMD_I2C)
                CONFIG_CMD_SETGETDCR      Support for DCR Register access
                                          (4xx only)
-               CONFIG_CMD_SHA1           print sha1 memory digest
+               CONFIG_CMD_SHA1SUM        print sha1 memory digest
                                          (requires CONFIG_CMD_MEMORY)
                CONFIG_CMD_SOURCE         "source" command Support
                CONFIG_CMD_SPI          * SPI serial bus support
@@ -865,6 +865,18 @@ The following options need to be configured:
                        Define this to use i/o functions instead of macros
                        (some hardware wont work with macros)
 
+               CONFIG_FTGMAC100
+               Support for Faraday's FTGMAC100 Gigabit SoC Ethernet
+
+                       CONFIG_FTGMAC100_EGIGA
+                       Define this to use GE link update with gigabit PHY.
+                       Define this if FTGMAC100 is connected to gigabit PHY.
+                       If your system has 10/100 PHY only, it might not occur
+                       wrong behavior. Because PHY usually return timeout or
+                       useless data when polling gigabit status and gigabit
+                       control registers. This behavior won't affect the
+                       correctnessof 10/100 link speed update.
+
                CONFIG_SMC911X
                Support for SMSC's LAN911x and LAN921x chips
 
@@ -2775,6 +2787,24 @@ Low Level (hardware related) configuration options:
                Disable PCI-Express on systems where it is supported but not
                required.
 
+- CONFIG_SYS_SRIO:
+               Chip has SRIO or not
+
+- CONFIG_SRIO1:
+               Board has SRIO 1 port available
+
+- CONFIG_SRIO2:
+               Board has SRIO 2 port available
+
+- CONFIG_SYS_SRIOn_MEM_VIRT:
+               Virtual Address of SRIO port 'n' memory region
+
+- CONFIG_SYS_SRIOn_MEM_PHYS:
+               Physical Address of SRIO port 'n' memory region
+
+- CONFIG_SYS_SRIOn_MEM_SIZE:
+               Size of SRIO port 'n' memory region
+
 - CONFIG_SPD_EEPROM
                Get DDR timing information from an I2C EEPROM. Common
                with pluggable memory modules such as SODIMMs