Revert "spi: add config option to enable the WP pin function on st micron flashes"

[u-boot] / README

diff --git a/README b/README
index caba4602bc7253af33d49244e0901e791b6e8547..82224f75e4964a21d92a425eb12e9de6508b5a5a 100644 (file)
--- a/README
+++ b/README
@@ -1947,6 +1947,26 @@ CBFS (Coreboot Filesystem) support
                the console jump but can help speed up operation when scrolling
                is slow.
 
+               CONFIG_LCD_ROTATION
+
+               Sometimes, for example if the display is mounted in portrait
+               mode or even if it's mounted landscape but rotated by 180degree,
+               we need to rotate our content of the display relative to the
+               framebuffer, so that user can read the messages which are
+               printed out.
+               Once CONFIG_LCD_ROTATION is defined, the lcd_console will be
+               initialized with a given rotation from "vl_rot" out of
+               "vidinfo_t" which is provided by the board specific code.
+               The value for vl_rot is coded as following (matching to
+               fbcon=rotate:<n> linux-kernel commandline):
+               0 = no rotation respectively 0 degree
+               1 = 90 degree rotation
+               2 = 180 degree rotation
+               3 = 270 degree rotation
+
+               If CONFIG_LCD_ROTATION is not defined, the console will be
+               initialized with 0degree rotation.
+
                CONFIG_LCD_BMP_RLE8
 
                Support drawing of RLE8-compressed bitmaps on the LCD.
@@ -3066,17 +3086,6 @@ CBFS (Coreboot Filesystem) support
                memories can be connected with a given cs line.
                Currently Xilinx Zynq qspi supports these type of connections.
 
-               CONFIG_SYS_SPI_ST_ENABLE_WP_PIN
-               enable the W#/Vpp signal to disable writing to the status
-               register on ST MICRON flashes like the N25Q128.
-               The status register write enable/disable bit, combined with
-               the W#/VPP signal provides hardware data protection for the
-               device as follows: When the enable/disable bit is set to 1,
-               and the W#/VPP signal is driven LOW, the status register
-               nonvolatile bits become read-only and the WRITE STATUS REGISTER
-               operation will not execute. The only way to exit this
-               hardware-protected mode is to drive W#/VPP HIGH.
-
 - SystemACE Support:
                CONFIG_SYSTEMACE