Revert "spi: add config option to enable the WP pin function on st micron flashes"

[u-boot] / README

diff --git a/README b/README
index fc1fd52f53053268fe3bdb4d7040dffc855a53f4..82224f75e4964a21d92a425eb12e9de6508b5a5a 100644 (file)
--- a/README
+++ b/README
@@ -3086,17 +3086,6 @@ CBFS (Coreboot Filesystem) support
                memories can be connected with a given cs line.
                Currently Xilinx Zynq qspi supports these type of connections.
 
-               CONFIG_SYS_SPI_ST_ENABLE_WP_PIN
-               enable the W#/Vpp signal to disable writing to the status
-               register on ST MICRON flashes like the N25Q128.
-               The status register write enable/disable bit, combined with
-               the W#/VPP signal provides hardware data protection for the
-               device as follows: When the enable/disable bit is set to 1,
-               and the W#/VPP signal is driven LOW, the status register
-               nonvolatile bits become read-only and the WRITE STATUS REGISTER
-               operation will not execute. The only way to exit this
-               hardware-protected mode is to drive W#/VPP HIGH.
-
 - SystemACE Support:
                CONFIG_SYSTEMACE