net: Remove all references to CONFIG_ETHADDR and friends

[u-boot] / README

diff --git a/README b/README
index a70af9864676652bd127fc1cdb1dfc7739472e96..a1f41f3519bf4ca0e2ab43fa13100309e4bd0875 100644 (file)
--- a/README
+++ b/README
@@ -1873,12 +1873,6 @@ CBFS (Coreboot Filesystem) support
                boot.  See the documentation file README.video for a
                description of this variable.
 
-               CONFIG_VIDEO_VGA
-
-               Enable the VGA video / BIOS for x86. The alternative if you
-               are using coreboot is to use the coreboot frame buffer
-               driver.
-
 
 - Keyboard Support:
                CONFIG_KEYBOARD
@@ -2113,18 +2107,6 @@ CBFS (Coreboot Filesystem) support
                Some PHY like Intel LXT971A need extra delay after
                command issued before MII status register can be read
 
-- Ethernet address:
-               CONFIG_ETHADDR
-               CONFIG_ETH1ADDR
-               CONFIG_ETH2ADDR
-               CONFIG_ETH3ADDR
-               CONFIG_ETH4ADDR
-               CONFIG_ETH5ADDR
-
-               Define a default value for Ethernet address to use
-               for the respective Ethernet interface, in case this
-               is not determined automatically.
-
 - IP address:
                CONFIG_IPADDR
 
@@ -2879,8 +2861,8 @@ CBFS (Coreboot Filesystem) support
                completely disabled. Anybody can change or delete
                these parameters.
 
-               Alternatively, if you #define _both_ CONFIG_ETHADDR
-               _and_ CONFIG_OVERWRITE_ETHADDR_ONCE, a default
+               Alternatively, if you define _both_ an ethaddr in the
+               default env _and_ CONFIG_OVERWRITE_ETHADDR_ONCE, a default
                Ethernet address is installed in the environment,
                which can be changed exactly ONCE by the user. [The
                serial# is unaffected by this, i. e. it remains
@@ -3096,17 +3078,6 @@ CBFS (Coreboot Filesystem) support
                memories can be connected with a given cs line.
                Currently Xilinx Zynq qspi supports these type of connections.
 
-               CONFIG_SYS_SPI_ST_ENABLE_WP_PIN
-               enable the W#/Vpp signal to disable writing to the status
-               register on ST MICRON flashes like the N25Q128.
-               The status register write enable/disable bit, combined with
-               the W#/VPP signal provides hardware data protection for the
-               device as follows: When the enable/disable bit is set to 1,
-               and the W#/VPP signal is driven LOW, the status register
-               nonvolatile bits become read-only and the WRITE STATUS REGISTER
-               operation will not execute. The only way to exit this
-               hardware-protected mode is to drive W#/VPP HIGH.
-
 - SystemACE Support:
                CONFIG_SYSTEMACE
 
@@ -5490,7 +5461,7 @@ loaded to, and "Flash Location" gives the image's address in NOR
 flash or offset in NAND flash.
 
 *Note* - these variables don't have to be defined for all boards, some
-boards currenlty use other variables for these purposes, and some
+boards currently use other variables for these purposes, and some
 boards use these variables for other purposes.
 
 Image              File Name        RAM Address       Flash Location
@@ -5640,7 +5611,8 @@ o If both the SROM and the environment contain a MAC address, and the
   warning is printed.
 
 o If neither SROM nor the environment contain a MAC address, an error
-  is raised.
+  is raised. If CONFIG_NET_RANDOM_ETHADDR is defined, then in this case
+  a random, locally-assigned MAC is used.
 
 If Ethernet drivers implement the 'write_hwaddr' function, valid MAC addresses
 will be programmed into hardware as part of the initialization process.         This