* (C) Copyright 2007
* Sascha Hauer, Pengutronix
*
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
+#include <div64.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/clock.h>
#include <asm/io.h>
+#include <asm/arch/sys_proto.h>
static u32 mx31_decode_pll(u32 reg, u32 infreq)
{
u32 mfi = GET_PLL_MFI(reg);
- u32 mfn = GET_PLL_MFN(reg);
+ s32 mfn = GET_PLL_MFN(reg);
u32 mfd = GET_PLL_MFD(reg);
u32 pd = GET_PLL_PD(reg);
mfi = mfi <= 5 ? 5 : mfi;
+ mfn = mfn >= 512 ? mfn - 1024 : mfn;
mfd += 1;
pd += 1;
- return ((2 * (infreq >> 10) * (mfi * mfd + mfn)) /
- (mfd * pd)) << 10;
+ return lldiv(2 * (u64)infreq * (mfi * mfd + mfn),
+ mfd * pd);
}
static u32 mx31_get_mpl_dpdgck_clk(void)
u32 infreq;
if ((readl(CCM_CCMR) & CCMR_PRCS_MASK) == CCMR_FPM)
- infreq = CONFIG_MX31_CLK32 * 1024;
+ infreq = MXC_CLK32 * 1024;
else
- infreq = CONFIG_MX31_HCLK_FREQ;
+ infreq = MXC_HCLK;
return mx31_decode_pll(readl(CCM_MPCTL), infreq);
}
void mx31_dump_clocks(void)
{
u32 cpufreq = mx31_get_mcu_main_clk();
- printf("mx31 cpu clock: %dMHz\n",cpufreq / 1000000);
+ printf("mx31 cpu clock: %dMHz\n", cpufreq / 1000000);
printf("ipg clock : %dHz\n", mx31_get_ipg_clk());
printf("hsp clock : %dHz\n", mx31_get_hsp_clk());
}
case MXC_IPG_PERCLK:
case MXC_CSPI_CLK:
case MXC_UART_CLK:
+ case MXC_ESDHC_CLK:
+ case MXC_I2C_CLK:
return mx31_get_ipg_clk();
case MXC_IPU_CLK:
return mx31_get_hsp_clk();
}
+void mx31_set_gpr(enum iomux_gp_func gp, char en)
+{
+ u32 l;
+ struct iomuxc_regs *iomuxc = (struct iomuxc_regs *)IOMUXC_BASE;
+
+ l = readl(&iomuxc->gpr);
+ if (en)
+ l |= gp;
+ else
+ l &= ~gp;
+
+ writel(l, &iomuxc->gpr);
+}
+
+void mxc_setup_weimcs(int cs, const struct mxc_weimcs *weimcs)
+{
+ struct mx31_weim *weim = (struct mx31_weim *) WEIM_BASE;
+ struct mx31_weim_cscr *cscr = &weim->cscr[cs];
+
+ writel(weimcs->upper, &cscr->upper);
+ writel(weimcs->lower, &cscr->lower);
+ writel(weimcs->additional, &cscr->additional);
+}
+
struct mx3_cpu_type mx31_cpu_type[] = {
{ .srev = 0x00, .v = 0x10 },
{ .srev = 0x10, .v = 0x11 },
return "WDOG";
case 0x0006:
return "JTAG";
+ case 0x0007:
+ return "ARM11P power gating";
default:
return "unknown reset";
}
}
#if defined(CONFIG_DISPLAY_CPUINFO)
-int print_cpuinfo (void)
+int print_cpuinfo(void)
{
u32 srev = get_cpu_rev();