/*
- * armboot - Startup Code for S3C6400/ARM1176 CPU-core
+ * armboot - Startup Code for ARM1176 CPU-core
*
* Copyright (c) 2007 Samsung Electronics
*
* Base codes by scsuh (sc.suh)
*/
+#include <asm-offsets.h>
#include <config.h>
#include <version.h>
-#ifdef CONFIG_ENABLE_MMU
-#include <asm/proc/domain.h>
-#endif
-#ifdef CONFIG_S3C64XX
-#include <asm/arch/s3c6400.h>
-#endif
-#if !defined(CONFIG_ENABLE_MMU) && !defined(CONFIG_SYS_PHY_UBOOT_BASE)
+#ifndef CONFIG_SYS_PHY_UBOOT_BASE
#define CONFIG_SYS_PHY_UBOOT_BASE CONFIG_SYS_UBOOT_BASE
#endif
.globl _start
_start: b reset
-#ifndef CONFIG_NAND_SPL
+#ifndef CONFIG_SPL_BUILD
ldr pc, _undefined_instruction
ldr pc, _software_interrupt
ldr pc, _prefetch_abort
*************************************************************************
*/
+.globl _TEXT_BASE
_TEXT_BASE:
- .word TEXT_BASE
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE)
+ .word CONFIG_SPL_TEXT_BASE
+#else
+ .word CONFIG_SYS_TEXT_BASE
+#endif
/*
- * Below variable is very important because we use MMU in U-Boot.
- * Without it, we cannot run code correctly before MMU is ON.
- * by scsuh.
+ * These are defined in the board-specific linker script.
+ * Subtracting _start from them lets the linker put their
+ * relative position in the executable instead of leaving
+ * them null.
*/
-_TEXT_PHY_BASE:
- .word CONFIG_SYS_PHY_UBOOT_BASE
-.globl _armboot_start
-_armboot_start:
- .word _start
+.globl _bss_start_ofs
+_bss_start_ofs:
+ .word __bss_start - _start
-/*
- * These are defined in the board-specific linker script.
- */
-.globl _bss_start
-_bss_start:
- .word __bss_start
+.globl _bss_end_ofs
+_bss_end_ofs:
+ .word __bss_end - _start
+
+.globl _end_ofs
+_end_ofs:
+ .word _end - _start
-.globl _bss_end
-_bss_end:
- .word _end
+/* IRQ stack memory (calculated at run-time) + 8 bytes */
+.globl IRQ_STACK_START_IN
+IRQ_STACK_START_IN:
+ .word 0x0badc0de
/*
* the actual reset code
* When booting from NAND - it has definitely been a reset, so, no need
* to flush caches and disable the MMU
*/
-#ifndef CONFIG_NAND_SPL
+#ifndef CONFIG_SPL_BUILD
/*
* flush v4 I/D caches
*/
bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM)
orr r0, r0, #0x00000002 @ set bit 2 (A) Align
orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache
+
/* Prepare to disable the MMU */
- adr r1, mmu_disable_phys
- /* We presume we're within the first 1024 bytes */
- and r1, r1, #0x3fc
- ldr r2, _TEXT_PHY_BASE
- ldr r3, =0xfff00000
- and r2, r2, r3
- orr r2, r2, r1
+ adr r2, mmu_disable_phys
+ sub r2, r2, #(CONFIG_SYS_PHY_UBOOT_BASE - CONFIG_SYS_TEXT_BASE)
b mmu_disable
.align 5
nop
nop
mov pc, r2
+mmu_disable_phys:
+
+#ifdef CONFIG_DISABLE_TCM
+ /*
+ * Disable the TCMs
+ */
+ mrc p15, 0, r0, c0, c0, 2 /* Return TCM details */
+ cmp r0, #0
+ beq skip_tcmdisable
+ mov r1, #0
+ mov r2, #1
+ tst r0, r2
+ mcrne p15, 0, r1, c9, c1, 1 /* Disable Instruction TCM if present*/
+ tst r0, r2, LSL #16
+ mcrne p15, 0, r1, c9, c1, 0 /* Disable Data TCM if present*/
+skip_tcmdisable:
+#endif
#endif
-mmu_disable_phys:
-#ifdef CONFIG_S3C64XX
+#ifdef CONFIG_PERIPORT_REMAP
/* Peri port setup */
- ldr r0, =0x70000000
- orr r0, r0, #0x13
- mcr p15,0,r0,c15,c2,4 @ 256M (0x70000000 - 0x7fffffff)
+ ldr r0, =CONFIG_PERIPORT_BASE
+ orr r0, r0, #CONFIG_PERIPORT_SIZE
+ mcr p15,0,r0,c15,c2,4
#endif
/*
*/
bl lowlevel_init /* go setup pll,mux,memory */
-after_copy:
-#ifdef CONFIG_ENABLE_MMU
-enable_mmu:
- /* enable domain access */
- ldr r5, =0x0000ffff
- mcr p15, 0, r5, c3, c0, 0 /* load domain access register */
-
- /* Set the TTB register */
- ldr r0, _mmu_table_base
- ldr r1, =CONFIG_SYS_PHY_UBOOT_BASE
- ldr r2, =0xfff00000
- bic r0, r0, r2
- orr r1, r0, r1
- mcr p15, 0, r1, c2, c0, 0
-
- /* Enable the MMU */
- mrc p15, 0, r0, c1, c0, 0
- orr r0, r0, #1 /* Set CR_M to enable MMU */
-
- /* Prepare to enable the MMU */
- adr r1, skip_hw_init
- and r1, r1, #0x3fc
- ldr r2, _TEXT_BASE
- ldr r3, =0xfff00000
- and r2, r2, r3
- orr r2, r2, r1
- b mmu_enable
-
- .align 5
- /* Run in a single cache-line */
-mmu_enable:
-
- mcr p15, 0, r0, c1, c0, 0
- nop
- nop
- mov pc, r2
-#endif
+ bl _main
-skip_hw_init:
- /* Set up the stack */
-stack_setup:
- ldr r0, =CONFIG_SYS_UBOOT_BASE /* base of copy in DRAM */
- sub r0, r0, #CONFIG_SYS_MALLOC_LEN /* malloc area */
- sub r0, r0, #CONFIG_SYS_GBL_DATA_SIZE /* bdinfo */
- sub sp, r0, #12 /* leave 3 words for abort-stack */
-
-clear_bss:
- ldr r0, _bss_start /* find start of bss segment */
- ldr r1, _bss_end /* stop here */
- mov r2, #0 /* clear */
-
-clbss_l:
- str r2, [r0] /* clear loop... */
- add r0, r0, #4
- cmp r0, r1
- ble clbss_l
-
-#ifndef CONFIG_NAND_SPL
- ldr pc, _start_armboot
-
-_start_armboot:
- .word start_armboot
-#else
- b nand_boot
-/* .word nand_boot*/
-#endif
+/*------------------------------------------------------------------------------*/
-#ifdef CONFIG_ENABLE_MMU
-_mmu_table_base:
- .word mmu_table
-#endif
+ .globl c_runtime_cpu_setup
+c_runtime_cpu_setup:
-#ifndef CONFIG_NAND_SPL
-/*
- * we assume that cache operation is done before. (eg. cleanup_before_linux())
- * actually, we don't need to do anything about cache if not use d-cache in
- * U-Boot. So, in this function we clean only MMU. by scsuh
- *
- * void theLastJump(void *kernel, int arch_num, uint boot_params);
- */
-#ifdef CONFIG_ENABLE_MMU
- .globl theLastJump
-theLastJump:
- mov r9, r0
- ldr r3, =0xfff00000
- ldr r4, _TEXT_PHY_BASE
- adr r5, phy_last_jump
- bic r5, r5, r3
- orr r5, r5, r4
- mov pc, r5
-phy_last_jump:
- /*
- * disable MMU stuff
- */
- mrc p15, 0, r0, c1, c0, 0
- bic r0, r0, #0x00002300 /* clear bits 13, 9:8 (--V- --RS) */
- bic r0, r0, #0x00000087 /* clear bits 7, 2:0 (B--- -CAM) */
- orr r0, r0, #0x00000002 /* set bit 2 (A) Align */
- orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */
- mcr p15, 0, r0, c1, c0, 0
+ mov pc, lr
- mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
-
- mov r0, #0
- mov pc, r9
-#endif
+#ifndef CONFIG_SPL_BUILD
/*
*************************************************************************
*
/* Save user registers (now in svc mode) r0-r12 */
stmia sp, {r0 - r12}
- ldr r2, _armboot_start
- sub r2, r2, #(CONFIG_SYS_MALLOC_LEN)
- /* set base 2 words into abort stack */
- sub r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE+8)
+ ldr r2, IRQ_STACK_START_IN
/* get values for "aborted" pc and cpsr (into parm regs) */
ldmia r2, {r2 - r3}
/* grab pointer to old stack */
.endm
.macro get_bad_stack
- /* setup our mode stack (enter in banked mode) */
- ldr r13, _armboot_start
- /* move past malloc pool */
- sub r13, r13, #(CONFIG_SYS_MALLOC_LEN)
- /* move to reserved a couple spots for abort stack */
- sub r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE + 8)
+ ldr r13, IRQ_STACK_START_IN @ setup our mode stack
/* save caller lr in position 0 of saved stack */
str lr, [r13]
sub r13, r13, #4
/* save R0's value. */
str r0, [r13]
- /* get data regions start */
- ldr r0, _armboot_start
- /* move past malloc pool */
- sub r0, r0, #(CONFIG_SYS_MALLOC_LEN)
- /* move past gbl and a couple spots for abort stack */
- sub r0, r0, #(CONFIG_SYS_GBL_DATA_SIZE + 8)
+ ldr r13, IRQ_STACK_START_IN @ setup our mode stack
/* save caller lr in position 0 of saved stack */
str lr, [r0]
/* get the spsr */
- mrs r0, spsr
+ mrs lr, spsr
/* save spsr in position 1 of saved stack */
str lr, [r0, #4]
+ /* restore lr */
+ ldr lr, [r0]
/* restore r0 */
ldr r0, [r13]
/* pop stack entry */
get_bad_stack
bad_save_user_regs
bl do_fiq
-#endif /* CONFIG_NAND_SPL */
+#endif /* CONFIG_SPL_BUILD */