ARM: uniphier: rework spl_boot_device() and related code

[u-boot] / arch / arm / cpu / arm926ejs / cache.c

diff --git a/arch/arm/cpu/arm926ejs/cache.c b/arch/arm/cpu/arm926ejs/cache.c
index 8d7873c9af332fc48a2dd511f0df7f7bfcf8e4be..02cb24c24ffb0c08b063f8a59f1181c57331e18e 100644 (file)
--- a/arch/arm/cpu/arm926ejs/cache.c
+++ b/arch/arm/cpu/arm926ejs/cache.c
@@ -8,11 +8,6 @@
 #include <common.h>
 
 #ifndef CONFIG_SYS_DCACHE_OFF
-
-#ifndef CONFIG_SYS_CACHELINE_SIZE
-#define CONFIG_SYS_CACHELINE_SIZE      32
-#endif
-
 void invalidate_dcache_all(void)
 {
        asm volatile("mcr p15, 0, %0, c7, c6, 0\n" : : "r"(0));
@@ -29,23 +24,6 @@ void flush_dcache_all(void)
        );
 }
 
-static int check_cache_range(unsigned long start, unsigned long stop)
-{
-       int ok = 1;
-
-       if (start & (CONFIG_SYS_CACHELINE_SIZE - 1))
-               ok = 0;
-
-       if (stop & (CONFIG_SYS_CACHELINE_SIZE - 1))
-               ok = 0;
-
-       if (!ok)
-               debug("CACHE: Misaligned operation at range [%08lx, %08lx]\n",
-                       start, stop);
-
-       return ok;
-}
-
 void invalidate_dcache_range(unsigned long start, unsigned long stop)
 {
        if (!check_cache_range(start, stop))
@@ -69,11 +47,6 @@ void flush_dcache_range(unsigned long start, unsigned long stop)
 
        asm volatile("mcr p15, 0, %0, c7, c10, 4\n" : : "r"(0));
 }
-
-void flush_cache(unsigned long start, unsigned long size)
-{
-       flush_dcache_range(start, start + size);
-}
 #else /* #ifndef CONFIG_SYS_DCACHE_OFF */
 void invalidate_dcache_all(void)
 {
@@ -82,21 +55,14 @@ void invalidate_dcache_all(void)
 void flush_dcache_all(void)
 {
 }
-
-void invalidate_dcache_range(unsigned long start, unsigned long stop)
-{
-}
-
-void flush_dcache_range(unsigned long start, unsigned long stop)
-{
-}
-
-void flush_cache(unsigned long start, unsigned long size)
-{
-}
 #endif /* #ifndef CONFIG_SYS_DCACHE_OFF */
 
 /*
  * Stub implementations for l2 cache operations
  */
+
 __weak void l2_cache_disable(void) {}
+
+#if defined CONFIG_SYS_THUMB_BUILD
+__weak void invalidate_l2_cache(void) {}
+#endif