*
* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
*
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
+#include <asm/arch/timer_defs.h>
+#include <div64.h>
-struct davinci_timer {
- u_int32_t pid12;
- u_int32_t emumgt;
- u_int32_t na1;
- u_int32_t na2;
- u_int32_t tim12;
- u_int32_t tim34;
- u_int32_t prd12;
- u_int32_t prd34;
- u_int32_t tcr;
- u_int32_t tgcr;
- u_int32_t wdtcr;
-};
+DECLARE_GLOBAL_DATA_PTR;
static struct davinci_timer * const timer =
(struct davinci_timer *)CONFIG_SYS_TIMERBASE;
-#define TIMER_LOAD_VAL (CONFIG_SYS_HZ_CLOCK / CONFIG_SYS_HZ)
-#define TIM_CLK_DIV 16
+#define TIMER_LOAD_VAL 0xffffffff
-static ulong timestamp;
-static ulong lastinc;
+#define TIM_CLK_DIV 16
int timer_init(void)
{
writel(0x06 | ((TIM_CLK_DIV - 1) << 8), &timer->tgcr);
writel(0x0, &timer->tim34);
writel(TIMER_LOAD_VAL, &timer->prd34);
- lastinc = 0;
- timestamp = 0;
writel(2 << 22, &timer->tcr);
+ gd->arch.timer_rate_hz = CONFIG_SYS_HZ_CLOCK / TIM_CLK_DIV;
+ gd->arch.timer_reset_value = 0;
return(0);
}
-void reset_timer(void)
+/*
+ * Get the current 64 bit timer tick count
+ */
+unsigned long long get_ticks(void)
{
- writel(0x0, &timer->tcr);
- writel(0x0, &timer->tim34);
- lastinc = 0;
- timestamp = 0;
- writel(2 << 22, &timer->tcr);
-}
+ unsigned long now = readl(&timer->tim34);
-static ulong get_timer_raw(void)
-{
- ulong now = readl(&timer->tim34);
-
- if (now >= lastinc) {
- /* normal mode */
- timestamp += now - lastinc;
- } else {
- /* overflow ... */
- timestamp += now + TIMER_LOAD_VAL - lastinc;
- }
- lastinc = now;
- return timestamp;
+ /* increment tbu if tbl has rolled over */
+ if (now < gd->arch.tbl)
+ gd->arch.tbu++;
+ gd->arch.tbl = now;
+
+ return (((unsigned long long)gd->arch.tbu) << 32) | gd->arch.tbl;
}
ulong get_timer(ulong base)
{
- return((get_timer_raw() / (TIMER_LOAD_VAL / TIM_CLK_DIV)) - base);
-}
+ unsigned long long timer_diff;
-void set_timer(ulong t)
-{
- timestamp = t;
+ timer_diff = get_ticks() - gd->arch.timer_reset_value;
+
+ return lldiv(timer_diff,
+ (gd->arch.timer_rate_hz / CONFIG_SYS_HZ)) - base;
}
void __udelay(unsigned long usec)
{
- ulong tmo;
- ulong endtime;
- signed long diff;
+ unsigned long long endtime;
- tmo = CONFIG_SYS_HZ_CLOCK / 1000;
- tmo *= usec;
- tmo /= (1000 * TIM_CLK_DIV);
+ endtime = lldiv((unsigned long long)usec * gd->arch.timer_rate_hz,
+ 1000000UL);
+ endtime += get_ticks();
- endtime = get_timer_raw() + tmo;
-
- do {
- ulong now = get_timer_raw();
- diff = endtime - now;
- } while (diff >= 0);
+ while (get_ticks() < endtime)
+ ;
}
/*
- * This function is derived from PowerPC code (read timebase as long long).
- * On ARM it just returns the timer value.
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
*/
-unsigned long long get_ticks(void)
+ulong get_tbclk(void)
{
- return(get_timer(0));
+ return gd->arch.timer_rate_hz;
}
+#ifdef CONFIG_HW_WATCHDOG
+static struct davinci_timer * const wdttimer =
+ (struct davinci_timer *)CONFIG_SYS_WDTTIMERBASE;
+
/*
- * This function is derived from PowerPC code (timebase clock frequency).
- * On ARM it returns the number of timer ticks per second.
+ * See prufw2.pdf for using Timer as a WDT
*/
-ulong get_tbclk(void)
+void davinci_hw_watchdog_enable(void)
+{
+ writel(0x0, &wdttimer->tcr);
+ writel(0x0, &wdttimer->tgcr);
+ /* TIMMODE = 2h */
+ writel(0x08 | 0x03 | ((TIM_CLK_DIV - 1) << 8), &wdttimer->tgcr);
+ writel(CONFIG_SYS_WDT_PERIOD_LOW, &wdttimer->prd12);
+ writel(CONFIG_SYS_WDT_PERIOD_HIGH, &wdttimer->prd34);
+ writel(2 << 22, &wdttimer->tcr);
+ writel(0x0, &wdttimer->tim12);
+ writel(0x0, &wdttimer->tim34);
+ /* set WDEN bit, WDKEY 0xa5c6 */
+ writel(0xa5c64000, &wdttimer->wdtcr);
+ /* clear counter register */
+ writel(0xda7e4000, &wdttimer->wdtcr);
+}
+
+void davinci_hw_watchdog_reset(void)
{
- return CONFIG_SYS_HZ;
+ writel(0xa5c64000, &wdttimer->wdtcr);
+ writel(0xda7e4000, &wdttimer->wdtcr);
}
+#endif
projects / u-boot / blobdiff