SPDX: Convert all of our single license tags to Linux Kernel style

[u-boot] / arch / arm / cpu / arm926ejs / lpc32xx / clk.c

diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/clk.c b/arch/arm/cpu/arm926ejs/lpc32xx/clk.c
index b7a44d59dac31d8c46c8c5fc67a9965b868fc8ad..5eb630dabe959a28f5093db5da4f2358ebbcb957 100644 (file)
--- a/arch/arm/cpu/arm926ejs/lpc32xx/clk.c
+++ b/arch/arm/cpu/arm926ejs/lpc32xx/clk.c
@@ -1,7 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright (C) 2011 by Vladimir Zapolskiy <vz@mleia.com>
- *
- * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #include <common.h>
@@ -54,12 +53,12 @@ unsigned int get_hclk_pll_rate(void)
        if (fref > 27000000ULL || fref < 1000000ULL)
                return 0;
 
-       fout = fref * m_div;
-       if (val & CLK_HCLK_PLL_FEEDBACK) {
-               fcco = fout;
+       fcco = fref * m_div;
+       fout = fcco;
+       if (val & CLK_HCLK_PLL_FEEDBACK)
+               fcco *= p_div;
+       else
                do_div(fout, p_div);
-       } else
-               fcco = fout * p_div;
 
        if (fcco > 320000000ULL || fcco < 156000000ULL)
                return 0;
@@ -98,6 +97,40 @@ unsigned int get_periph_clk_rate(void)
        return get_hclk_pll_rate() / get_periph_clk_div();
 }
 
+unsigned int get_sdram_clk_rate(void)
+{
+       unsigned int src_clk;
+
+       if (!(readl(&clk->pwr_ctrl) & CLK_PWR_NORMAL_RUN))
+               return get_sys_clk_rate();
+
+       src_clk = get_hclk_pll_rate();
+
+       if (readl(&clk->sdramclk_ctrl) & CLK_SDRAM_DDR_SEL) {
+               /* using DDR */
+               switch (readl(&clk->hclkdiv_ctrl) & CLK_HCLK_DDRAM_MASK) {
+               case CLK_HCLK_DDRAM_HALF:
+                       return src_clk/2;
+               case CLK_HCLK_DDRAM_NOMINAL:
+                       return src_clk;
+               default:
+                       return 0;
+               }
+       } else {
+               /* using SDR */
+               switch (readl(&clk->hclkdiv_ctrl) & CLK_HCLK_ARM_PLL_DIV_MASK) {
+               case CLK_HCLK_ARM_PLL_DIV_4:
+                       return src_clk/4;
+               case CLK_HCLK_ARM_PLL_DIV_2:
+                       return src_clk/2;
+               case CLK_HCLK_ARM_PLL_DIV_1:
+                       return src_clk;
+               default:
+                       return 0;
+               }
+       }
+}
+
 int get_serial_clock(void)
 {
        return get_periph_clk_rate();