Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq

[u-boot] / arch / arm / cpu / arm926ejs / mxs / spl_mem_init.c

diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c b/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c
index 07db27927f47aaaa22b9cb9e72eb272d953b91c1..97ef67d8c5843b06fcd6c7d903cd3d4cb21d976b 100644 (file)
--- a/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c
+++ b/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c
@@ -4,23 +4,7 @@
  * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
  * on behalf of DENX Software Engineering GmbH
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #include <common.h>
@@ -256,9 +240,14 @@ static void mx23_mem_setup_vddmem(void)
        struct mxs_power_regs *power_regs =
                (struct mxs_power_regs *)MXS_POWER_BASE;
 
+       /* We must wait before and after disabling the current limiter! */
+       early_delay(10000);
+
        clrbits_le32(&power_regs->hw_power_vddmemctrl,
                POWER_VDDMEMCTRL_ENABLE_ILIMIT);
 
+       early_delay(10000);
+
 }
 
 static void mx23_mem_init(void)
@@ -285,7 +274,13 @@ static void mx23_mem_init(void)
        setbits_le32(MXS_DRAM_BASE + 0x20, 1 << 16);
 
        clrbits_le32(MXS_DRAM_BASE + 0x40, 1 << 17);
-       early_delay(20000);
+
+       /* Wait for EMI_STAT bit DRAM_HALTED */
+       for (;;) {
+               if (!(readl(MXS_EMI_BASE + 0x10) & (1 << 1)))
+                       break;
+               early_delay(1000);
+       }
 
        /* Adjust EMI port priority. */
        clrsetbits_le32(0x80020000, 0x1f << 16, 0x2);