Merge branch 'master' of git://www.denx.de/git/u-boot-imx

[u-boot] / arch / arm / cpu / arm926ejs / mxs / spl_power_init.c

diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c b/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c
index 7fb734e9dc0159a53a97c25ddb2cbd3bac81c744..1ec8e2b6438beba535b5f2ff10de62a978cbf64b 100644 (file)
--- a/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c
+++ b/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c
@@ -14,6 +14,13 @@
 
 #include "mxs_init.h"
 
+#ifdef CONFIG_SYS_MXS_VDD5V_ONLY
+#define DCDC4P2_DROPOUT_CONFIG POWER_DCDC4P2_DROPOUT_CTRL_100MV | \
+                               POWER_DCDC4P2_DROPOUT_CTRL_SRC_4P2
+#else
+#define DCDC4P2_DROPOUT_CONFIG POWER_DCDC4P2_DROPOUT_CTRL_100MV | \
+                               POWER_DCDC4P2_DROPOUT_CTRL_SRC_SEL
+#endif
 /**
  * mxs_power_clock2xtal() - Switch CPU core clock source to 24MHz XTAL
  *
@@ -240,6 +247,39 @@ static void mxs_power_setup_5v_detect(void)
                        POWER_5VCTRL_PWRUP_VBUS_CMPS);
 }
 
+/**
+ * mxs_power_switch_dcdc_clocksource() - Switch PLL clock for DC-DC converters
+ * @freqsel:   One of the POWER_MISC_FREQSEL_xxx defines to select the clock
+ *
+ * This function configures and then enables an alternative PLL clock source
+ * for the DC-DC converters.
+ */
+void mxs_power_switch_dcdc_clocksource(uint32_t freqsel)
+{
+       struct mxs_power_regs *power_regs =
+               (struct mxs_power_regs *)MXS_POWER_BASE;
+
+       /* Select clocksource for DC-DC converters */
+       clrsetbits_le32(&power_regs->hw_power_misc,
+                       POWER_MISC_FREQSEL_MASK,
+                       freqsel);
+       setbits_le32(&power_regs->hw_power_misc,
+                       POWER_MISC_SEL_PLLCLK);
+}
+
+/**
+ * mxs_power_setup_dcdc_clocksource() - Setup PLL clock source for DC-DC converters
+ *
+ * Normally, there is no need to switch DC-DC clocksource. This is the reason,
+ * why this function is a stub and does nothing. However, boards can implement
+ * this function when required and call mxs_power_switch_dcdc_clocksource() to
+ * switch to an alternative clock source.
+ */
+__weak void mxs_power_setup_dcdc_clocksource(void)
+{
+       debug("SPL: Using default DC-DC clocksource\n");
+}
+
 /**
  * mxs_src_power_init() - Preconfigure the power block
  *
@@ -303,8 +343,7 @@ static void mxs_power_init_4p2_params(void)
 
        clrsetbits_le32(&power_regs->hw_power_dcdc4p2,
                POWER_DCDC4P2_DROPOUT_CTRL_MASK,
-               POWER_DCDC4P2_DROPOUT_CTRL_100MV |
-               POWER_DCDC4P2_DROPOUT_CTRL_SRC_SEL);
+               DCDC4P2_DROPOUT_CONFIG);
 
        clrsetbits_le32(&power_regs->hw_power_5vctrl,
                POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK,
@@ -326,6 +365,11 @@ static void mxs_enable_4p2_dcdc_input(int xfer)
 
        debug("SPL: %s 4P2 DC-DC Input\n", xfer ? "Enabling" : "Disabling");
 
+       if (xfer && (readl(&power_regs->hw_power_5vctrl) &
+                       POWER_5VCTRL_ENABLE_DCDC)) {
+               return;
+       }
+
        prev_5v_brnout = readl(&power_regs->hw_power_5vctrl) &
                                POWER_5VCTRL_PWDN_5VBRNOUT;
        prev_5v_droop = readl(&power_regs->hw_power_ctrl) &
@@ -337,11 +381,6 @@ static void mxs_enable_4p2_dcdc_input(int xfer)
 
        clrbits_le32(&power_regs->hw_power_ctrl, POWER_CTRL_ENIRQ_VDD5V_DROOP);
 
-       if (xfer && (readl(&power_regs->hw_power_5vctrl) &
-                       POWER_5VCTRL_ENABLE_DCDC)) {
-               return;
-       }
-
        /*
         * Recording orignal values that will be modified temporarlily
         * to handle a chip bug. See chip errata for CQ ENGR00115837
@@ -866,6 +905,7 @@ static void mxs_power_configure_power_source(void)
 
        debug("SPL: Configuring power source\n");
 
+       mxs_power_setup_dcdc_clocksource();
        mxs_src_power_init();
 
        if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
@@ -1215,8 +1255,8 @@ void mxs_power_init(void)
        debug("SPL: Setting VDDIO to 3V3 (brownout @ 3v15)\n");
        mxs_power_set_vddx(&mxs_vddio_cfg, 3300, 3150);
 
-       debug("SPL: Setting VDDD to 1V5 (brownout @ 1v0)\n");
-       mxs_power_set_vddx(&mxs_vddd_cfg, 1500, 1000);
+       debug("SPL: Setting VDDD to 1V5 (brownout @ 1v315)\n");
+       mxs_power_set_vddx(&mxs_vddd_cfg, 1500, 1315);
 #ifdef CONFIG_MX23
        debug("SPL: Setting mx23 VDDMEM to 2V5 (brownout @ 1v7)\n");
        mxs_power_set_vddx(&mxs_vddmem_cfg, 2500, 1700);