/*
- * Copyright (C) 2010 Albert ARIBAUD <albert.aribaud@free.fr>
+ * Copyright (C) 2010 Albert ARIBAUD <albert.u.boot@aribaud.net>
*
* Based on original Kirkwood support which is
* (C) Copyright 2009
* Marvell Semiconductor <www.marvell.com>
* Written-by: Prafulla Wadaskar <prafulla@marvell.com>
*
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301 USA
+ * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <netdev.h>
#include <asm/cache.h>
+#include <asm/io.h>
#include <u-boot/md5.h>
-#include <asm/arch/orion5x.h>
-#include <hush.h>
+#include <asm/arch/cpu.h>
#define BUFLEN 16
}
/*
- * Window Size
+ * Compute Window Size field value from size expressed in bytes
* Used with the Base register to set the address window size and location.
* Must be programmed from LSB to MSB as sequence of ones followed by
* sequence of zeros. The number of ones specifies the size of the window in
- * 64 KByte granularity (e.g., a value of 0x00FF specifies 256 = 16 MByte).
- * NOTE: A value of 0x0 specifies 64-KByte size.
+ * 64 KiB granularity (e.g., a value of 0x00FF specifies 256 = 16 MiB).
+ * NOTES:
+ * 1) A sizeval equal to 0x0 specifies 4 GiB.
+ * 2) A return value of 0x0 specifies 64 KiB.
*/
unsigned int orion5x_winctrl_calcsize(unsigned int sizeval)
{
- int i;
- unsigned int j = 0;
- u32 val = sizeval >> 1;
-
- for (i = 0; val > 0x10000; i++) {
- j |= (1 << i);
- val = val >> 1;
- }
- return 0x0000ffff & j;
+ /*
+ * Calculate the number of 64 KiB blocks needed minus one (rounding up).
+ * For sizeval > 0 this is equivalent to:
+ * sizeval = (u32) ceil((double) sizeval / 65536.0) - 1
+ */
+ sizeval = (sizeval - 1) >> 16;
+
+ /*
+ * Propagate 'one' bits to the right by 'oring' them.
+ * We need only treat bits 15-0.
+ */
+ sizeval |= sizeval >> 1; /* 'Or' bit 15 onto bit 14 */
+ sizeval |= sizeval >> 2; /* 'Or' bits 15-14 onto bits 13-12 */
+ sizeval |= sizeval >> 4; /* 'Or' bits 15-12 onto bits 11-8 */
+ sizeval |= sizeval >> 8; /* 'Or' bits 15-8 onto bits 7-0*/
+
+ return sizeval;
}
/*
*
* If remap function not used, remap_lo must be set as base
*
+ * NOTES:
+ *
+ * 1) in order to avoid windows with inconsistent control and base values
+ * (which could prevent access to BOOTCS and hence execution from FLASH)
+ * always disable window before writing the base value then reenable it
+ * by writing the control value.
+ *
+ * 2) in order to avoid losing access to BOOTCS when disabling window 7,
+ * first configure window 6 for BOOTCS, then configure window 7 for BOOTCS,
+ * then configure windows 6 for its own target.
+ *
* Reference Documentation:
* Mbus-L to Mbus Bridge Registers Configuration.
* (Sec 25.1 and 25.3 of Datasheet)
struct orion5x_win_registers *winregs =
(struct orion5x_win_registers *)ORION5X_CPU_WIN_BASE;
- /* Window 0: PCIE MEM address space */
- writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_DEFSZ_PCIE_MEM,
+/* Disable window 0, configure it for its intended target, enable it. */
+ writel(0, &winregs[0].ctrl);
+ writel(ORION5X_ADR_PCIE_MEM, &winregs[0].base);
+ writel(ORION5X_ADR_PCIE_MEM_REMAP_LO, &winregs[0].remap_lo);
+ writel(ORION5X_ADR_PCIE_MEM_REMAP_HI, &winregs[0].remap_hi);
+ writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_PCIE_MEM,
ORION5X_TARGET_PCIE, ORION5X_ATTR_PCIE_MEM,
ORION5X_WIN_ENABLE), &winregs[0].ctrl);
- writel(ORION5X_DEFADR_PCIE_MEM, &winregs[0].base);
- writel(ORION5X_DEFADR_PCIE_MEM_REMAP_LO, &winregs[0].remap_lo);
- writel(ORION5X_DEFADR_PCIE_MEM_REMAP_HI, &winregs[0].remap_hi);
-
- /* Window 1: PCIE IO address space */
- writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_DEFSZ_PCIE_IO,
+/* Disable window 1, configure it for its intended target, enable it. */
+ writel(0, &winregs[1].ctrl);
+ writel(ORION5X_ADR_PCIE_IO, &winregs[1].base);
+ writel(ORION5X_ADR_PCIE_IO_REMAP_LO, &winregs[1].remap_lo);
+ writel(ORION5X_ADR_PCIE_IO_REMAP_HI, &winregs[1].remap_hi);
+ writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_PCIE_IO,
ORION5X_TARGET_PCIE, ORION5X_ATTR_PCIE_IO,
ORION5X_WIN_ENABLE), &winregs[1].ctrl);
- writel(ORION5X_DEFADR_PCIE_IO, &winregs[1].base);
- writel(ORION5X_DEFADR_PCIE_IO_REMAP_LO, &winregs[1].remap_lo);
- writel(ORION5X_DEFADR_PCIE_IO_REMAP_HI, &winregs[1].remap_hi);
-
- /* Window 2: PCI MEM address space */
- writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_DEFSZ_PCI_MEM,
+/* Disable window 2, configure it for its intended target, enable it. */
+ writel(0, &winregs[2].ctrl);
+ writel(ORION5X_ADR_PCI_MEM, &winregs[2].base);
+ writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_PCI_MEM,
ORION5X_TARGET_PCI, ORION5X_ATTR_PCI_MEM,
ORION5X_WIN_ENABLE), &winregs[2].ctrl);
- writel(ORION5X_DEFADR_PCI_MEM, &winregs[2].base);
-
- /* Window 3: PCI IO address space */
- writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_DEFSZ_PCI_IO,
+/* Disable window 3, configure it for its intended target, enable it. */
+ writel(0, &winregs[3].ctrl);
+ writel(ORION5X_ADR_PCI_IO, &winregs[3].base);
+ writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_PCI_IO,
ORION5X_TARGET_PCI, ORION5X_ATTR_PCI_IO,
ORION5X_WIN_ENABLE), &winregs[3].ctrl);
- writel(ORION5X_DEFADR_PCI_IO, &winregs[3].base);
-
- /* Window 4: DEV_CS0 address space */
- writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_DEFSZ_DEV_CS0,
+/* Disable window 4, configure it for its intended target, enable it. */
+ writel(0, &winregs[4].ctrl);
+ writel(ORION5X_ADR_DEV_CS0, &winregs[4].base);
+ writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_DEV_CS0,
ORION5X_TARGET_DEVICE, ORION5X_ATTR_DEV_CS0,
ORION5X_WIN_ENABLE), &winregs[4].ctrl);
- writel(ORION5X_DEFADR_DEV_CS0, &winregs[4].base);
-
- /* Window 5: DEV_CS1 address space */
- writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_DEFSZ_DEV_CS1,
+/* Disable window 5, configure it for its intended target, enable it. */
+ writel(0, &winregs[5].ctrl);
+ writel(ORION5X_ADR_DEV_CS1, &winregs[5].base);
+ writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_DEV_CS1,
ORION5X_TARGET_DEVICE, ORION5X_ATTR_DEV_CS1,
ORION5X_WIN_ENABLE), &winregs[5].ctrl);
- writel(ORION5X_DEFADR_DEV_CS1, &winregs[5].base);
-
- /* Window 6: DEV_CS2 address space */
- writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_DEFSZ_DEV_CS2,
- ORION5X_TARGET_DEVICE, ORION5X_ATTR_DEV_CS2,
+/* Disable window 6, configure it for FLASH, enable it. */
+ writel(0, &winregs[6].ctrl);
+ writel(ORION5X_ADR_BOOTROM, &winregs[6].base);
+ writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_BOOTROM,
+ ORION5X_TARGET_DEVICE, ORION5X_ATTR_BOOTROM,
ORION5X_WIN_ENABLE), &winregs[6].ctrl);
- writel(ORION5X_DEFADR_DEV_CS2, &winregs[6].base);
-
- /* Window 7: BOOT Memory address space */
- writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_DEFSZ_BOOTROM,
+/* Disable window 7, configure it for FLASH, enable it. */
+ writel(0, &winregs[7].ctrl);
+ writel(ORION5X_ADR_BOOTROM, &winregs[7].base);
+ writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_BOOTROM,
ORION5X_TARGET_DEVICE, ORION5X_ATTR_BOOTROM,
ORION5X_WIN_ENABLE), &winregs[7].ctrl);
- writel(ORION5X_DEFADR_BOOTROM, &winregs[7].base);
+/* Disable window 6, configure it for its intended target, enable it. */
+ writel(0, &winregs[6].ctrl);
+ writel(ORION5X_ADR_DEV_CS2, &winregs[6].base);
+ writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_DEV_CS2,
+ ORION5X_TARGET_DEVICE, ORION5X_ATTR_DEV_CS2,
+ ORION5X_WIN_ENABLE), &winregs[6].ctrl);
return 0;
}
*/
int print_cpuinfo(void)
{
- char dev_str[] = "0x0000";
- char rev_str[] = "0x00";
+ char dev_str[7]; /* room enough for 0x0000 plus null byte */
+ char rev_str[5]; /* room enough for 0x00 plus null byte */
char *dev_name = NULL;
char *rev_name = NULL;
writel(ORION5X_MPP0_7, ORION5X_MPP_BASE+0x00);
writel(ORION5X_MPP8_15, ORION5X_MPP_BASE+0x04);
writel(ORION5X_MPP16_23, ORION5X_MPP_BASE+0x50);
+ writel(ORION5X_GPIO_OUT_VALUE, ORION5X_GPIO_BASE+0x00);
writel(ORION5X_GPIO_OUT_ENABLE, ORION5X_GPIO_BASE+0x04);
+ writel(ORION5X_GPIO_IN_POLARITY, ORION5X_GPIO_BASE+0x0c);
+ /* initialize timer */
+ timer_init_r();
return 0;
}
#endif /* CONFIG_ARCH_MISC_INIT */
+
+#ifdef CONFIG_MVGBE
+int cpu_eth_init(bd_t *bis)
+{
+ mvgbe_initialize(bis);
+ return 0;
+}
+#endif
projects / u-boot / blobdiff