arm: Fixed the offset for the no relocation.

[u-boot] / arch / arm / cpu / arm926ejs / start.S

diff --git a/arch/arm/cpu/arm926ejs/start.S b/arch/arm/cpu/arm926ejs/start.S
index 525c1122c96b5a005f5ca47d3901be20bb46a627..2188f7e35d1df8de3bce8d9ccadea6e60bc89b46 100644 (file)
--- a/arch/arm/cpu/arm926ejs/start.S
+++ b/arch/arm/cpu/arm926ejs/start.S
@@ -215,6 +215,7 @@ call_board_init_f:
 
 /*------------------------------------------------------------------------------*/
 
+#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_NAND_SPL)
 /*
  * void relocate_code (addr_sp, gd, addr_moni)
  *
@@ -235,6 +236,7 @@ stack_setup:
        adr     r0, _start
        sub     r9, r6, r0              /* r9 <- relocation offset */
        cmp     r0, r6
+       moveq   r9, #0          /* no relocation. relocation offset(r9) = 0 */
        beq     clear_bss               /* skip relocation */
        mov     r1, r6                  /* r1 <- scratch for copy loop */
        ldr     r3, _bss_start_ofs
@@ -344,6 +346,7 @@ _rel_dyn_end_ofs:
        .word __rel_dyn_end - _start
 _dynsym_start_ofs:
        .word __dynsym_start - _start
+#endif
 
 /*
  *************************************************************************
@@ -369,7 +372,8 @@ flush_dcache:
        mcr     p15, 0, r0, c7, c5, 0   /* invalidate I Cache */
 
        /*
-        * disable MMU and D cache, and enable I cache
+        * disable MMU and D cache
+        * enable I cache if CONFIG_SYS_ICACHE_OFF is not defined
         */
        mrc     p15, 0, r0, c1, c0, 0
        bic     r0, r0, #0x00000300     /* clear bits 9:8 (---- --RS) */
@@ -380,7 +384,9 @@ flush_dcache:
        bic     r0, r0, #0x00002000     /* clear bit 13 (--V- ----) */
 #endif
        orr     r0, r0, #0x00000002     /* set bit 2 (A) Align */
+#ifndef CONFIG_SYS_ICACHE_OFF
        orr     r0, r0, #0x00001000     /* set bit 12 (I) I-Cache */
+#endif
        mcr     p15, 0, r0, c1, c0, 0
 
        /*