arm: rmobile: Add cpu_eth_init function

[u-boot] / arch / arm / cpu / arm926ejs / start.S

diff --git a/arch/arm/cpu/arm926ejs/start.S b/arch/arm/cpu/arm926ejs/start.S
index 16e35c288c1a9257021b8e579f86b3f14e6949fe..521d46290cfb47fdeb8dd1071ad1cdf187141b1e 100644 (file)
--- a/arch/arm/cpu/arm926ejs/start.S
+++ b/arch/arm/cpu/arm926ejs/start.S
@@ -51,9 +51,18 @@
  */
 
 
+#ifdef CONFIG_SYS_DV_NOR_BOOT_CFG
 .globl _start
 _start:
+.globl _NOR_BOOT_CFG
+_NOR_BOOT_CFG:
+       .word   CONFIG_SYS_DV_NOR_BOOT_CFG
        b       reset
+#else
+.globl _start
+_start:
+       b       reset
+#endif
 #ifdef CONFIG_SPL_BUILD
 /* No exception handlers in preloader */
        ldr     pc, _hang
@@ -117,7 +126,15 @@ _fiq:
 
 .globl _TEXT_BASE
 _TEXT_BASE:
+#ifdef CONFIG_NAND_SPL /* deprecated, use instead CONFIG_SPL_BUILD */
        .word   CONFIG_SYS_TEXT_BASE
+#else
+#ifdef CONFIG_SPL_BUILD
+       .word   CONFIG_SPL_TEXT_BASE
+#else
+       .word   CONFIG_SYS_TEXT_BASE
+#endif
+#endif
 
 /*
  * These are defined in the board-specific linker script.
@@ -137,6 +154,12 @@ _bss_end_ofs:
 _end_ofs:
        .word _end - _start
 
+#ifdef CONFIG_NAND_U_BOOT
+.globl _end
+_end:
+       .word __bss_end__
+#endif
+
 #ifdef CONFIG_USE_IRQ
 /* IRQ stack memory (calculated at run-time) */
 .globl IRQ_STACK_START
@@ -177,13 +200,22 @@ reset:
 
 /* Set stackpointer in internal RAM to call board_init_f */
 call_board_init_f:
+#ifdef CONFIG_NAND_SPL /* deprecated, use instead CONFIG_SPL_BUILD */
+       ldr     sp, =(CONFIG_SYS_INIT_SP_ADDR)
+#else
+#ifdef CONFIG_SPL_BUILD
+       ldr     sp, =(CONFIG_SPL_STACK)
+#else
        ldr     sp, =(CONFIG_SYS_INIT_SP_ADDR)
+#endif
+#endif
        bic     sp, sp, #7 /* 8-byte alignment for ABI compliance */
        ldr     r0,=0x00000000
        bl      board_init_f
 
 /*------------------------------------------------------------------------------*/
 
+#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_NAND_SPL)
 /*
  * void relocate_code (addr_sp, gd, addr_moni)
  *
@@ -202,6 +234,7 @@ stack_setup:
        mov     sp, r4
 
        adr     r0, _start
+       sub     r9, r6, r0              /* r9 <- relocation offset */
        cmp     r0, r6
        beq     clear_bss               /* skip relocation */
        mov     r1, r6                  /* r1 <- scratch for copy loop */
@@ -256,21 +289,29 @@ fixnext:
 #endif
 
 clear_bss:
-#ifndef CONFIG_SPL_BUILD
+#ifdef CONFIG_SPL_BUILD
+       /* No relocation for SPL */
+       ldr     r0, =__bss_start
+       ldr     r1, =__bss_end__
+#else
        ldr     r0, _bss_start_ofs
        ldr     r1, _bss_end_ofs
        mov     r4, r6                  /* reloc addr */
        add     r0, r0, r4
        add     r1, r1, r4
+#endif
        mov     r2, #0x00000000         /* clear                            */
 
-clbss_l:str    r2, [r0]                /* clear loop...                    */
+clbss_l:cmp    r0, r1                  /* clear loop... */
+       bhs     clbss_e                 /* if reached end of bss, exit */
+       str     r2, [r0]
        add     r0, r0, #4
-       cmp     r0, r1
-       bne     clbss_l
+       b       clbss_l
+clbss_e:
 
+#ifndef CONFIG_SPL_BUILD
        bl coloured_LED_init
-       bl red_LED_on
+       bl red_led_on
 #endif
 
 /*
@@ -304,6 +345,7 @@ _rel_dyn_end_ofs:
        .word __rel_dyn_end - _start
 _dynsym_start_ofs:
        .word __dynsym_start - _start
+#endif
 
 /*
  *************************************************************************
@@ -318,20 +360,32 @@ _dynsym_start_ofs:
 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
 cpu_init_crit:
        /*
-        * flush v4 I/D caches
+        * flush D cache before disabling it
         */
        mov     r0, #0
-       mcr     p15, 0, r0, c7, c7, 0   /* flush v3/v4 cache */
-       mcr     p15, 0, r0, c8, c7, 0   /* flush v4 TLB */
+flush_dcache:
+       mrc     p15, 0, r15, c7, c10, 3
+       bne     flush_dcache
+
+       mcr     p15, 0, r0, c8, c7, 0   /* invalidate TLB */
+       mcr     p15, 0, r0, c7, c5, 0   /* invalidate I Cache */
 
        /*
-        * disable MMU stuff and caches
+        * disable MMU and D cache
+        * enable I cache if CONFIG_SYS_ICACHE_OFF is not defined
         */
        mrc     p15, 0, r0, c1, c0, 0
-       bic     r0, r0, #0x00002300     /* clear bits 13, 9:8 (--V- --RS) */
+       bic     r0, r0, #0x00000300     /* clear bits 9:8 (---- --RS) */
        bic     r0, r0, #0x00000087     /* clear bits 7, 2:0 (B--- -CAM) */
+#ifdef CONFIG_SYS_EXCEPTION_VECTORS_HIGH
+       orr     r0, r0, #0x00002000     /* set bit 13 (--V- ----) */
+#else
+       bic     r0, r0, #0x00002000     /* clear bit 13 (--V- ----) */
+#endif
        orr     r0, r0, #0x00000002     /* set bit 2 (A) Align */
+#ifndef CONFIG_SYS_ICACHE_OFF
        orr     r0, r0, #0x00001000     /* set bit 12 (I) I-Cache */
+#endif
        mcr     p15, 0, r0, c1, c0, 0
 
        /*