mx31: Define default SoC input clock frequencies

[u-boot] / arch / arm / cpu / arm946es / start.S

diff --git a/arch/arm/cpu/arm946es/start.S b/arch/arm/cpu/arm946es/start.S
index 00914f42e9cde5829426cb21f1a6eff66acf2889..b4d1d2dd1c6f8e701ad51e97e0310109362f8295 100644 (file)
--- a/arch/arm/cpu/arm946es/start.S
+++ b/arch/arm/cpu/arm946es/start.S
@@ -5,12 +5,12 @@
  *
  *  ----- Adapted for OMAP1610 OMAP730 from ARM925t code ------
  *
- *  Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
- *  Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
+ *  Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
+ *  Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
  *  Copyright (c) 2002 Gary Jennejohn <garyj@denx.de>
  *  Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com>
  *  Copyright (c) 2003 Kshitij <kshitij@ti.com>
- *  Copyright (c) 2010 Albert Aribaud <albert.aribaud@free.fr>
+ *  Copyright (c) 2010 Albert Aribaud <albert.u.boot@aribaud.net>
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -186,7 +186,7 @@ copy_loop:
        cmp     r0, r2                  /* until source end address [r2]    */
        blo     copy_loop
 
-#ifndef CONFIG_PRELOADER
+#ifndef CONFIG_SPL_BUILD
        /*
         * fix .rel.dyn relocations
         */
@@ -228,7 +228,7 @@ fixnext:
 #endif
 
 clear_bss:
-#ifndef CONFIG_PRELOADER
+#ifndef CONFIG_SPL_BUILD
        ldr     r0, _bss_start_ofs
        ldr     r1, _bss_end_ofs
        mov     r4, r6                  /* reloc addr */
@@ -236,10 +236,12 @@ clear_bss:
        add     r1, r1, r4
        mov     r2, #0x00000000         /* clear                            */
 
-clbss_l:str    r2, [r0]                /* clear loop...                    */
+clbss_l:cmp    r0, r1                  /* clear loop... */
+       bhs     clbss_e                 /* if reached end of bss, exit */
+       str     r2, [r0]
        add     r0, r0, #4
-       cmp     r0, r1
-       blo     clbss_l
+       b       clbss_l
+clbss_e:
 #endif
 
 /*