Merge branch 'master' of git://git.denx.de/u-boot-usb

[u-boot] / arch / arm / cpu / armv7 / am33xx / board.c

diff --git a/arch/arm/cpu/armv7/am33xx/board.c b/arch/arm/cpu/armv7/am33xx/board.c
index 4634a9ab4fd9013fb6580a2bc92a4a3e49baaf4a..b387ac27ec8c39ced1ae14b084df0190fbf007d4 100644 (file)
--- a/arch/arm/cpu/armv7/am33xx/board.c
+++ b/arch/arm/cpu/armv7/am33xx/board.c
@@ -25,10 +25,11 @@
 #include <asm/arch/clock.h>
 #include <asm/arch/gpio.h>
 #include <asm/arch/mmc_host_def.h>
-#include <asm/arch/common_def.h>
+#include <asm/arch/sys_proto.h>
 #include <asm/io.h>
 #include <asm/omap_common.h>
 #include <asm/emif.h>
+#include <asm/gpio.h>
 #include <i2c.h>
 #include <miiphy.h>
 #include <cpsw.h>
@@ -52,31 +53,21 @@ const struct gpio_bank *const omap_gpio_bank = gpio_bank_am33xx;
 #define MII_MODE_ENABLE                0x0
 #define RGMII_MODE_ENABLE      0xA
 
-static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
+/* GPIO that controls power to DDR on EVM-SK */
+#define GPIO_DDR_VTT_EN                7
 
-/*
- * I2C Address of on-board EEPROM
- */
-#define I2C_BASE_BOARD_ADDR    0x50
-
-#define NO_OF_MAC_ADDR          3
-#define ETH_ALEN               6
-#define NAME_LEN               8
-
-struct am335x_baseboard_id {
-       unsigned int  magic;
-       char name[NAME_LEN];
-       char version[4];
-       char serial[12];
-       char config[32];
-       char mac_addr[NO_OF_MAC_ADDR][ETH_ALEN];
-};
+static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
 
-static struct am335x_baseboard_id header;
+static struct am335x_baseboard_id __attribute__((section (".data"))) header;
 
 static inline int board_is_bone(void)
 {
-       return !strncmp(header.name, "A335BONE", NAME_LEN);
+       return !strncmp(header.name, "A335BONE", HDR_NAME_LEN);
+}
+
+static inline int board_is_evm_sk(void)
+{
+       return !strncmp("A335X_SK", header.name, HDR_NAME_LEN);
 }
 
 /*
@@ -85,14 +76,14 @@ static inline int board_is_bone(void)
 static int read_eeprom(void)
 {
        /* Check if baseboard eeprom is available */
-       if (i2c_probe(I2C_BASE_BOARD_ADDR)) {
+       if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {
                puts("Could not probe the EEPROM; something fundamentally "
                        "wrong on the I2C bus.\n");
                return -ENODEV;
        }
 
        /* read the eeprom using i2c */
-       if (i2c_read(I2C_BASE_BOARD_ADDR, 0, 2, (uchar *)&header,
+       if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)&header,
                                                        sizeof(header))) {
                puts("Could not read the EEPROM; something fundamentally"
                        " wrong on the I2C bus.\n");
@@ -104,8 +95,8 @@ static int read_eeprom(void)
                 * read the eeprom using i2c again,
                 * but use only a 1 byte address
                 */
-               if (i2c_read(I2C_BASE_BOARD_ADDR, 0, 1, (uchar *)&header,
-                                                       sizeof(header))) {
+               if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1,
+                                       (uchar *)&header, sizeof(header))) {
                        puts("Could not read the EEPROM; something "
                                "fundamentally wrong on the I2C bus.\n");
                        return -EIO;
@@ -144,6 +135,18 @@ static void init_timer(void)
 }
 #endif
 
+/*
+ * Determine what type of DDR we have.
+ */
+static short inline board_memory_type(void)
+{
+       /* The following boards are known to use DDR3. */
+       if (board_is_evm_sk())
+               return EMIF_REG_SDRAM_TYPE_DDR3;
+
+       return EMIF_REG_SDRAM_TYPE_DDR2;
+}
+
 /*
  * early system init of muxing and clocks.
  */
@@ -185,17 +188,36 @@ void s_init(void)
 
        preloader_console_init();
 
-       config_ddr(EMIF_REG_SDRAM_TYPE_DDR2);
-#endif
+       /* Initalize the board header */
+       enable_i2c0_pin_mux();
+       i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+       if (read_eeprom() < 0)
+               puts("Could not get board ID.\n");
+
+       enable_board_pin_mux(&header);
+       if (board_is_evm_sk()) {
+               /*
+                * EVM SK 1.2A and later use gpio0_7 to enable DDR3.
+                * This is safe enough to do on older revs.
+                */
+               gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
+               gpio_direction_output(GPIO_DDR_VTT_EN, 1);
+       }
 
-       /* Enable MMC0 */
-       enable_mmc0_pin_mux();
+       config_ddr(board_memory_type());
+#endif
 }
 
 #if defined(CONFIG_OMAP_HSMMC) && !defined(CONFIG_SPL_BUILD)
 int board_mmc_init(bd_t *bis)
 {
-       return omap_mmc_init(0, 0, 0);
+       int ret;
+       
+       ret = omap_mmc_init(0, 0, 0);
+       if (ret)
+               return ret;
+
+       return omap_mmc_init(1, 0, 0);
 }
 #endif
 
@@ -206,14 +228,10 @@ void setup_clocks_for_console(void)
 }
 
 /*
- * Basic board specific setup
+ * Basic board specific setup.  Pinmux has been handled already.
  */
 int board_init(void)
 {
-       enable_uart0_pin_mux();
-
-       enable_i2c0_pin_mux();
-       enable_i2c1_pin_mux();
        i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
        if (read_eeprom() < 0)
                puts("Could not get board ID.\n");
@@ -286,12 +304,10 @@ int board_eth_init(bd_t *bis)
        }
 
        if (board_is_bone()) {
-               enable_mii1_pin_mux();
                writel(MII_MODE_ENABLE, &cdev->miisel);
                cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
                                PHY_INTERFACE_MODE_MII;
        } else {
-               enable_rgmii1_pin_mux();
                writel(RGMII_MODE_ENABLE, &cdev->miisel);
                cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
                                PHY_INTERFACE_MODE_RGMII;