Merge branch 'master' of git://git.denx.de/u-boot-usb

[u-boot] / arch / arm / cpu / armv7 / am33xx / clock.c

diff --git a/arch/arm/cpu/armv7/am33xx/clock.c b/arch/arm/cpu/armv7/am33xx/clock.c
index 4ca6c45349f5ea62c3d73a0328aa16c8ab119a7a..2b19506a341c01a39a5347aba4a76f865829689e 100644 (file)
--- a/arch/arm/cpu/armv7/am33xx/clock.c
+++ b/arch/arm/cpu/armv7/am33xx/clock.c
@@ -24,6 +24,7 @@
 
 #define PRCM_MOD_EN            0x2
 #define PRCM_FORCE_WAKEUP      0x2
+#define PRCM_FUNCTL            0x0
 
 #define PRCM_EMIF_CLK_ACTIVITY BIT(2)
 #define PRCM_L3_GCLK_ACTIVITY  BIT(4)
@@ -38,7 +39,7 @@
 #define CLK_MODE_SEL           0x7
 #define CLK_MODE_MASK          0xfffffff8
 #define CLK_DIV_SEL            0xFFFFFFE0
-
+#define CPGMAC0_IDLE           0x30000
 
 const struct cm_perpll *cmper = (struct cm_perpll *)CM_PER;
 const struct cm_wkuppll *cmwkup = (struct cm_wkuppll *)CM_WKUP;
@@ -70,6 +71,10 @@ static void enable_interface_clocks(void)
        writel(PRCM_MOD_EN, &cmper->l4hsclkctrl);
        while (readl(&cmper->l4hsclkctrl) != PRCM_MOD_EN)
                ;
+
+       writel(PRCM_MOD_EN, &cmwkup->wkgpio0clkctrl);
+       while (readl(&cmwkup->wkgpio0clkctrl) != PRCM_MOD_EN)
+               ;
 }
 
 /*
@@ -101,10 +106,53 @@ static void enable_per_clocks(void)
        while (readl(&cmper->timer2clkctrl) != PRCM_MOD_EN)
                ;
 
+       /* Select the Master osc 24 MHZ as Timer2 clock source */
+       writel(0x1, &cmdpll->clktimer2clk);
+
        /* UART0 */
        writel(PRCM_MOD_EN, &cmwkup->wkup_uart0ctrl);
        while (readl(&cmwkup->wkup_uart0ctrl) != PRCM_MOD_EN)
                ;
+
+       /* MMC0*/
+       writel(PRCM_MOD_EN, &cmper->mmc0clkctrl);
+       while (readl(&cmper->mmc0clkctrl) != PRCM_MOD_EN)
+               ;
+
+       /* i2c0 */
+       writel(PRCM_MOD_EN, &cmwkup->wkup_i2c0ctrl);
+       while (readl(&cmwkup->wkup_i2c0ctrl) != PRCM_MOD_EN)
+               ;
+
+       /* gpio1 module */
+       writel(PRCM_MOD_EN, &cmper->gpio1clkctrl);
+       while (readl(&cmper->gpio1clkctrl) != PRCM_MOD_EN)
+               ;
+
+       /* gpio2 module */
+       writel(PRCM_MOD_EN, &cmper->gpio2clkctrl);
+       while (readl(&cmper->gpio2clkctrl) != PRCM_MOD_EN)
+               ;
+
+       /* gpio3 module */
+       writel(PRCM_MOD_EN, &cmper->gpio3clkctrl);
+       while (readl(&cmper->gpio3clkctrl) != PRCM_MOD_EN)
+               ;
+
+       /* i2c1 */
+       writel(PRCM_MOD_EN, &cmper->i2c1clkctrl);
+       while (readl(&cmper->i2c1clkctrl) != PRCM_MOD_EN)
+               ;
+
+       /* Ethernet */
+       writel(PRCM_MOD_EN, &cmper->cpgmac0clkctrl);
+       while ((readl(&cmper->cpgmac0clkctrl) & CPGMAC0_IDLE) != PRCM_FUNCTL)
+               ;
+
+       /* spi0 */
+       writel(PRCM_MOD_EN, &cmper->spi0clkctrl);
+       while (readl(&cmper->spi0clkctrl) != PRCM_MOD_EN)
+               ;
 }
 
 static void mpu_pll_config(void)
@@ -203,7 +251,7 @@ static void per_pll_config(void)
                ;
 }
 
-static void ddr_pll_config(void)
+void ddr_pll_config(unsigned int ddrpll_m)
 {
        u32 clkmode, clksel, div_m2;
 
@@ -221,7 +269,7 @@ static void ddr_pll_config(void)
                ;
 
        clksel = clksel & (~CLK_SEL_MASK);
-       clksel = clksel | ((DDRPLL_M << CLK_SEL_SHIFT) | DDRPLL_N);
+       clksel = clksel | ((ddrpll_m << CLK_SEL_SHIFT) | DDRPLL_N);
        writel(clksel, &cmwkup->clkseldpllddr);
 
        div_m2 = div_m2 & CLK_DIV_SEL;
@@ -242,11 +290,6 @@ void enable_emif_clocks(void)
        writel(PRCM_MOD_EN, &cmper->emiffwclkctrl);
        /* Enable EMIF0 Clock */
        writel(PRCM_MOD_EN, &cmper->emifclkctrl);
-       /* Poll for emif_gclk  & L3_G clock  are active */
-       while ((readl(&cmper->l3clkstctrl) & (PRCM_EMIF_CLK_ACTIVITY |
-                       PRCM_L3_GCLK_ACTIVITY)) != (PRCM_EMIF_CLK_ACTIVITY |
-                       PRCM_L3_GCLK_ACTIVITY))
-               ;
        /* Poll if module is functional */
        while ((readl(&cmper->emifclkctrl)) != PRCM_MOD_EN)
                ;
@@ -260,7 +303,6 @@ void pll_init()
        mpu_pll_config();
        core_pll_config();
        per_pll_config();
-       ddr_pll_config();
 
        /* Enable the required interconnect clocks */
        enable_interface_clocks();