#define CLK_MODE_MASK 0xfffffff8
#define CLK_DIV_SEL 0xFFFFFFE0
#define CPGMAC0_IDLE 0x30000
+#define DPLL_CLKDCOLDO_GATE_CTRL 0x300
const struct cm_perpll *cmper = (struct cm_perpll *)CM_PER;
const struct cm_wkuppll *cmwkup = (struct cm_wkuppll *)CM_WKUP;
const struct cm_dpll *cmdpll = (struct cm_dpll *)CM_DPLL;
+const struct cm_rtc *cmrtc = (struct cm_rtc *)CM_RTC;
static void enable_interface_clocks(void)
{
while (readl(&cmwkup->wkup_uart0ctrl) != PRCM_MOD_EN)
;
+ /* UART1 */
+#ifdef CONFIG_SERIAL2
+ writel(PRCM_MOD_EN, &cmper->uart1clkctrl);
+ while (readl(&cmper->uart1clkctrl) != PRCM_MOD_EN)
+ ;
+#endif /* CONFIG_SERIAL2 */
+
+ /* UART2 */
+#ifdef CONFIG_SERIAL3
+ writel(PRCM_MOD_EN, &cmper->uart2clkctrl);
+ while (readl(&cmper->uart2clkctrl) != PRCM_MOD_EN)
+ ;
+#endif /* CONFIG_SERIAL3 */
+
+ /* UART3 */
+#ifdef CONFIG_SERIAL4
+ writel(PRCM_MOD_EN, &cmper->uart3clkctrl);
+ while (readl(&cmper->uart3clkctrl) != PRCM_MOD_EN)
+ ;
+#endif /* CONFIG_SERIAL4 */
+
+ /* UART4 */
+#ifdef CONFIG_SERIAL5
+ writel(PRCM_MOD_EN, &cmper->uart4clkctrl);
+ while (readl(&cmper->uart4clkctrl) != PRCM_MOD_EN)
+ ;
+#endif /* CONFIG_SERIAL5 */
+
+ /* UART5 */
+#ifdef CONFIG_SERIAL6
+ writel(PRCM_MOD_EN, &cmper->uart5clkctrl);
+ while (readl(&cmper->uart5clkctrl) != PRCM_MOD_EN)
+ ;
+#endif /* CONFIG_SERIAL6 */
+
+ /* GPMC */
+ writel(PRCM_MOD_EN, &cmper->gpmcclkctrl);
+ while (readl(&cmper->gpmcclkctrl) != PRCM_MOD_EN)
+ ;
+
+ /* ELM */
+ writel(PRCM_MOD_EN, &cmper->elmclkctrl);
+ while (readl(&cmper->elmclkctrl) != PRCM_MOD_EN)
+ ;
+
/* MMC0*/
writel(PRCM_MOD_EN, &cmper->mmc0clkctrl);
while (readl(&cmper->mmc0clkctrl) != PRCM_MOD_EN)
writel(PRCM_MOD_EN, &cmper->spi0clkctrl);
while (readl(&cmper->spi0clkctrl) != PRCM_MOD_EN)
;
+
+ /* RTC */
+ writel(PRCM_MOD_EN, &cmrtc->rtcclkctrl);
+ while (readl(&cmrtc->rtcclkctrl) != PRCM_MOD_EN)
+ ;
+
+ /* MUSB */
+ writel(PRCM_MOD_EN, &cmper->usb0clkctrl);
+ while (readl(&cmper->usb0clkctrl) != PRCM_MOD_EN)
+ ;
}
static void mpu_pll_config(void)
while (readl(&cmwkup->idlestdpllper) != ST_DPLL_CLK)
;
+
+ writel(DPLL_CLKDCOLDO_GATE_CTRL, &cmwkup->clkdcoldodpllper);
}
void ddr_pll_config(unsigned int ddrpll_m)