ARM: DRA7-evm: DDR3: Update leveling values

[u-boot] / arch / arm / cpu / armv7 / am33xx / clock_am43xx.c

diff --git a/arch/arm/cpu/armv7/am33xx/clock_am43xx.c b/arch/arm/cpu/armv7/am33xx/clock_am43xx.c
index c4890f2b432e080f02c36127397cd1c0ef8a3c87..31188c85bccb7fcd69644c185494752993551ea8 100644 (file)
--- a/arch/arm/cpu/armv7/am33xx/clock_am43xx.c
+++ b/arch/arm/cpu/armv7/am33xx/clock_am43xx.c
@@ -18,6 +18,7 @@
 
 struct cm_perpll *const cmper = (struct cm_perpll *)CM_PER;
 struct cm_wkuppll *const cmwkup = (struct cm_wkuppll *)CM_WKUP;
+struct cm_dpll *const cmdpll = (struct cm_dpll *)CM_DPLL;
 
 const struct dpll_regs dpll_mpu_regs = {
        .cm_clkmode_dpll        = CM_WKUP + 0x560,
@@ -47,17 +48,13 @@ const struct dpll_regs dpll_ddr_regs = {
        .cm_idlest_dpll         = CM_WKUP + 0x5A4,
        .cm_clksel_dpll         = CM_WKUP + 0x5AC,
        .cm_div_m2_dpll         = CM_WKUP + 0x5B0,
+       .cm_div_m4_dpll         = CM_WKUP + 0x5B8,
 };
 
-const struct dpll_params dpll_mpu = {
-               -1, -1, -1, -1, -1, -1, -1};
-const struct dpll_params dpll_core = {
-               -1, -1, -1, -1, -1, -1, -1};
-const struct dpll_params dpll_per = {
-               -1, -1, -1, -1, -1, -1, -1};
-
 void setup_clocks_for_console(void)
 {
+       u32 clkctrl, idlest = MODULE_CLKCTRL_IDLEST_DISABLED;
+
        /* Do not add any spl_debug prints in this function */
        clrsetbits_le32(&cmwkup->wkclkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK,
                        CD_CLKCTRL_CLKTRCTRL_SW_WKUP <<
@@ -68,6 +65,13 @@ void setup_clocks_for_console(void)
                        MODULE_CLKCTRL_MODULEMODE_MASK,
                        MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
                        MODULE_CLKCTRL_MODULEMODE_SHIFT);
+
+       while ((idlest == MODULE_CLKCTRL_IDLEST_DISABLED) ||
+               (idlest == MODULE_CLKCTRL_IDLEST_TRANSITIONING)) {
+               clkctrl = readl(&cmwkup->wkup_uart0ctrl);
+               idlest = (clkctrl & MODULE_CLKCTRL_IDLEST_MASK) >>
+                        MODULE_CLKCTRL_IDLEST_SHIFT;
+       }
 }
 
 void enable_basic_clocks(void)
@@ -99,12 +103,19 @@ void enable_basic_clocks(void)
                &cmper->gpio1clkctrl,
                &cmper->gpio2clkctrl,
                &cmper->gpio3clkctrl,
+               &cmper->gpio4clkctrl,
+               &cmper->gpio5clkctrl,
                &cmper->i2c1clkctrl,
+               &cmper->cpgmac0clkctrl,
                &cmper->emiffwclkctrl,
                &cmper->emifclkctrl,
                &cmper->otfaemifclkctrl,
+               &cmper->qspiclkctrl,
                0
        };
 
        do_enable_clocks(clk_domains, clk_modules_explicit_en, 1);
+
+       /* Select the Master osc clk as Timer2 clock source */
+       writel(0x1, &cmdpll->clktimer2clk);
 }