Merge remote-tracking branch 'mpc83xx/next'

[u-boot] / arch / arm / cpu / armv7 / cache_v7.c

diff --git a/arch/arm/cpu/armv7/cache_v7.c b/arch/arm/cpu/armv7/cache_v7.c
index 3e1e1bf8779bc5d88eb5e9c8e9b67159c0962099..5f6d0396f3af877c5cbc7abf4eef9f16c28a9699 100644 (file)
--- a/arch/arm/cpu/armv7/cache_v7.c
+++ b/arch/arm/cpu/armv7/cache_v7.c
@@ -81,8 +81,8 @@ static void v7_inval_dcache_level_setway(u32 level, u32 num_sets,
                                        : : "r" (setway));
                }
        }
-       /* DMB to make sure the operation is complete */
-       CP15DMB;
+       /* DSB to make sure the operation is complete */
+       CP15DSB;
 }
 
 static void v7_clean_inval_dcache_level_setway(u32 level, u32 num_sets,
@@ -108,8 +108,8 @@ static void v7_clean_inval_dcache_level_setway(u32 level, u32 num_sets,
                                        : : "r" (setway));
                }
        }
-       /* DMB to make sure the operation is complete */
-       CP15DMB;
+       /* DSB to make sure the operation is complete */
+       CP15DSB;
 }
 
 static void v7_maint_dcache_level_setway(u32 level, u32 operation)
@@ -181,21 +181,23 @@ static void v7_dcache_inval_range(u32 start, u32 stop, u32 line_len)
        u32 mva;
 
        /*
-        * If start address is not aligned to cache-line flush the first
-        * line to prevent affecting somebody else's buffer
+        * If start address is not aligned to cache-line do not
+        * invalidate the first cache-line
         */
        if (start & (line_len - 1)) {
-               v7_dcache_clean_inval_range(start, start + 1, line_len);
+               printf("ERROR: %s - start address is not aligned - 0x%08x\n",
+                       __func__, start);
                /* move to next cache line */
                start = (start + line_len - 1) & ~(line_len - 1);
        }
 
        /*
-        * If stop address is not aligned to cache-line flush the last
-        * line to prevent affecting somebody else's buffer
+        * If stop address is not aligned to cache-line do not
+        * invalidate the last cache-line
         */
        if (stop & (line_len - 1)) {
-               v7_dcache_clean_inval_range(stop, stop + 1, line_len);
+               printf("ERROR: %s - stop address is not aligned - 0x%08x\n",
+                       __func__, stop);
                /* align to the beginning of this cache line */
                stop &= ~(line_len - 1);
        }
@@ -227,8 +229,8 @@ static void v7_dcache_maint_range(u32 start, u32 stop, u32 range_op)
                break;
        }
 
-       /* DMB to make sure the operation is complete */
-       CP15DMB;
+       /* DSB to make sure the operation is complete */
+       CP15DSB;
 }
 
 /* Invalidate TLB */
@@ -295,6 +297,12 @@ void arm_init_before_mmu(void)
        v7_inval_tlb();
 }
 
+void mmu_page_table_flush(unsigned long start, unsigned long stop)
+{
+       flush_dcache_range(start, stop);
+       v7_inval_tlb();
+}
+
 /*
  * Flush range from all levels of d-cache/unified-cache used:
  * Affects the range [start, start + size - 1]
@@ -327,6 +335,11 @@ void arm_init_before_mmu(void)
 void  flush_cache(unsigned long start, unsigned long size)
 {
 }
+
+void mmu_page_table_flush(unsigned long start, unsigned long stop)
+{
+}
+
 #endif /* #ifndef CONFIG_SYS_DCACHE_OFF */
 
 #ifndef CONFIG_SYS_ICACHE_OFF