Merge branch 'master' of git://git.denx.de/u-boot-video

[u-boot] / arch / arm / cpu / armv7 / cache_v7.c

diff --git a/arch/arm/cpu/armv7/cache_v7.c b/arch/arm/cpu/armv7/cache_v7.c
index 0f9d8377ed5ac568d996257647c9137d6fa60477..a5aa4fa6436ca719505c04472bb3b60bc67c7d4f 100644 (file)
--- a/arch/arm/cpu/armv7/cache_v7.c
+++ b/arch/arm/cpu/armv7/cache_v7.c
@@ -68,7 +68,7 @@ static void v7_inval_dcache_level_setway(u32 level, u32 num_sets,
                }
        }
        /* DSB to make sure the operation is complete */
-       CP15DSB;
+       DSB;
 }
 
 static void v7_clean_inval_dcache_level_setway(u32 level, u32 num_sets,
@@ -96,7 +96,7 @@ static void v7_clean_inval_dcache_level_setway(u32 level, u32 num_sets,
                }
        }
        /* DSB to make sure the operation is complete */
-       CP15DSB;
+       DSB;
 }
 
 static void v7_maint_dcache_level_setway(u32 level, u32 operation)
@@ -215,7 +215,7 @@ static void v7_dcache_maint_range(u32 start, u32 stop, u32 range_op)
        }
 
        /* DSB to make sure the operation is complete */
-       CP15DSB;
+       DSB;
 }
 
 /* Invalidate TLB */
@@ -228,9 +228,9 @@ static void v7_inval_tlb(void)
        /* Invalidate entire instruction TLB */
        asm volatile ("mcr p15, 0, %0, c8, c5, 0" : : "r" (0));
        /* Full system DSB - make sure that the invalidation is complete */
-       CP15DSB;
+       DSB;
        /* Full system ISB - make sure the instruction stream sees it */
-       CP15ISB;
+       ISB;
 }
 
 void invalidate_dcache_all(void)
@@ -286,15 +286,6 @@ void mmu_page_table_flush(unsigned long start, unsigned long stop)
        flush_dcache_range(start, stop);
        v7_inval_tlb();
 }
-
-/*
- * Flush range from all levels of d-cache/unified-cache used:
- * Affects the range [start, start + size - 1]
- */
-void  flush_cache(unsigned long start, unsigned long size)
-{
-       flush_dcache_range(start, start + size);
-}
 #else /* #ifndef CONFIG_SYS_DCACHE_OFF */
 void invalidate_dcache_all(void)
 {
@@ -304,22 +295,10 @@ void flush_dcache_all(void)
 {
 }
 
-void invalidate_dcache_range(unsigned long start, unsigned long stop)
-{
-}
-
-void flush_dcache_range(unsigned long start, unsigned long stop)
-{
-}
-
 void arm_init_before_mmu(void)
 {
 }
 
-void  flush_cache(unsigned long start, unsigned long size)
-{
-}
-
 void mmu_page_table_flush(unsigned long start, unsigned long stop)
 {
 }
@@ -343,10 +322,10 @@ void invalidate_icache_all(void)
        asm volatile ("mcr p15, 0, %0, c7, c5, 6" : : "r" (0));
 
        /* Full system DSB - make sure that the invalidation is complete */
-       CP15DSB;
+       DSB;
 
        /* ISB - make sure the instruction stream sees it */
-       CP15ISB;
+       ISB;
 }
 #else
 void invalidate_icache_all(void)