Exynos: clock: add CLK_DIV_FSYS3 at set_mmc_clk

[u-boot] / arch / arm / cpu / armv7 / exynos / clock.c

diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c
index ae6d7fe0d9b985a1f6bb92b2413910a035b1911a..956427c9ebbfe9dd9a9ed8b763ecd25c7f75482e 100644 (file)
--- a/arch/arm/cpu/armv7/exynos/clock.c
+++ b/arch/arm/cpu/armv7/exynos/clock.c
@@ -484,6 +484,100 @@ static unsigned long exynos5_get_uart_clk(int dev_index)
        return uclk;
 }
 
+static unsigned long exynos4_get_mmc_clk(int dev_index)
+{
+       struct exynos4_clock *clk =
+               (struct exynos4_clock *)samsung_get_base_clock();
+       unsigned long uclk, sclk;
+       unsigned int sel, ratio, pre_ratio;
+       int shift;
+
+       sel = readl(&clk->src_fsys);
+       sel = (sel >> (dev_index << 2)) & 0xf;
+
+       if (sel == 0x6)
+               sclk = get_pll_clk(MPLL);
+       else if (sel == 0x7)
+               sclk = get_pll_clk(EPLL);
+       else if (sel == 0x8)
+               sclk = get_pll_clk(VPLL);
+       else
+               return 0;
+
+       switch (dev_index) {
+       case 0:
+       case 1:
+               ratio = readl(&clk->div_fsys1);
+               pre_ratio = readl(&clk->div_fsys1);
+               break;
+       case 2:
+       case 3:
+               ratio = readl(&clk->div_fsys2);
+               pre_ratio = readl(&clk->div_fsys2);
+               break;
+       case 4:
+               ratio = readl(&clk->div_fsys3);
+               pre_ratio = readl(&clk->div_fsys3);
+               break;
+       default:
+               return 0;
+       }
+
+       if (dev_index == 1 || dev_index == 3)
+               shift = 16;
+
+       ratio = (ratio >> shift) & 0xf;
+       pre_ratio = (pre_ratio >> (shift + 8)) & 0xff;
+       uclk = (sclk / (ratio + 1)) / (pre_ratio + 1);
+
+       return uclk;
+}
+
+static unsigned long exynos5_get_mmc_clk(int dev_index)
+{
+       struct exynos5_clock *clk =
+               (struct exynos5_clock *)samsung_get_base_clock();
+       unsigned long uclk, sclk;
+       unsigned int sel, ratio, pre_ratio;
+       int shift;
+
+       sel = readl(&clk->src_fsys);
+       sel = (sel >> (dev_index << 2)) & 0xf;
+
+       if (sel == 0x6)
+               sclk = get_pll_clk(MPLL);
+       else if (sel == 0x7)
+               sclk = get_pll_clk(EPLL);
+       else if (sel == 0x8)
+               sclk = get_pll_clk(VPLL);
+       else
+               return 0;
+
+       switch (dev_index) {
+       case 0:
+       case 1:
+               ratio = readl(&clk->div_fsys1);
+               pre_ratio = readl(&clk->div_fsys1);
+               break;
+       case 2:
+       case 3:
+               ratio = readl(&clk->div_fsys2);
+               pre_ratio = readl(&clk->div_fsys2);
+               break;
+       default:
+               return 0;
+       }
+
+       if (dev_index == 1 || dev_index == 3)
+               shift = 16;
+
+       ratio = (ratio >> shift) & 0xf;
+       pre_ratio = (pre_ratio >> (shift + 8)) & 0xff;
+       uclk = (sclk / (ratio + 1)) / (pre_ratio + 1);
+
+       return uclk;
+}
+
 /* exynos4: set the mmc clock */
 static void exynos4_set_mmc_clk(int dev_index, unsigned int div)
 {
@@ -497,9 +591,14 @@ static void exynos4_set_mmc_clk(int dev_index, unsigned int div)
         * MMC0_PRE_RATIO [15:8], MMC1_PRE_RATIO [31:24]
         * CLK_DIV_FSYS2
         * MMC2_PRE_RATIO [15:8], MMC3_PRE_RATIO [31:24]
+        * CLK_DIV_FSYS3
+        * MMC4_PRE_RATIO [15:8]
         */
        if (dev_index < 2) {
                addr = (unsigned int)&clk->div_fsys1;
+       }  else if (dev_index == 4) {
+               addr = (unsigned int)&clk->div_fsys3;
+               dev_index -= 4;
        } else {
                addr = (unsigned int)&clk->div_fsys2;
                dev_index -= 2;
@@ -741,7 +840,7 @@ void exynos5_set_lcd_clk(void)
         */
        cfg = readl(&clk->src_disp1_0);
        cfg &= ~(0xf);
-       cfg |= 0x8;
+       cfg |= 0x6;
        writel(cfg, &clk->src_disp1_0);
 
        /*
@@ -1130,6 +1229,14 @@ unsigned long get_uart_clk(int dev_index)
        }
 }
 
+unsigned long get_mmc_clk(int dev_index)
+{
+       if (cpu_is_exynos5())
+               return exynos5_get_mmc_clk(dev_index);
+       else
+               return exynos4_get_mmc_clk(dev_index);
+}
+
 void set_mmc_clk(int dev_index, unsigned int div)
 {
        if (cpu_is_exynos5())