]> git.sur5r.net Git - u-boot/blobdiff - arch/arm/cpu/armv7/exynos/clock.c
Merge branch 'u-boot/master'
[u-boot] / arch / arm / cpu / armv7 / exynos / clock.c
index 4fa1e23122922950be94754186a7d489d26759fc..df4d4739ffb1ca8c38aa989f4cf6c5e2977a4e51 100644 (file)
 #define PLL_DIV_1024   1024
 #define PLL_DIV_65535  65535
 #define PLL_DIV_65536  65536
-
 /* *
  * This structure is to store the src bit, div bit and prediv bit
  * positions of the peripheral clocks of the src and div registers
  */
 struct clk_bit_info {
        enum periph_id id;
+       int32_t src_mask;
+       int32_t div_mask;
+       int32_t prediv_mask;
        int8_t src_bit;
        int8_t div_bit;
        int8_t prediv_bit;
 };
 
-/* periph_id src_bit div_bit prediv_bit */
 static struct clk_bit_info exynos5_bit_info[] = {
-       {PERIPH_ID_UART0,       0,      0,      -1},
-       {PERIPH_ID_UART1,       4,      4,      -1},
-       {PERIPH_ID_UART2,       8,      8,      -1},
-       {PERIPH_ID_UART3,       12,     12,     -1},
-       {PERIPH_ID_I2C0,        -1,     24,     0},
-       {PERIPH_ID_I2C1,        -1,     24,     0},
-       {PERIPH_ID_I2C2,        -1,     24,     0},
-       {PERIPH_ID_I2C3,        -1,     24,     0},
-       {PERIPH_ID_I2C4,        -1,     24,     0},
-       {PERIPH_ID_I2C5,        -1,     24,     0},
-       {PERIPH_ID_I2C6,        -1,     24,     0},
-       {PERIPH_ID_I2C7,        -1,     24,     0},
-       {PERIPH_ID_SPI0,        16,     0,      8},
-       {PERIPH_ID_SPI1,        20,     16,     24},
-       {PERIPH_ID_SPI2,        24,     0,      8},
-       {PERIPH_ID_SDMMC0,      0,      0,      8},
-       {PERIPH_ID_SDMMC1,      4,      16,     24},
-       {PERIPH_ID_SDMMC2,      8,      0,      8},
-       {PERIPH_ID_SDMMC3,      12,     16,     24},
-       {PERIPH_ID_I2S0,        0,      0,      4},
-       {PERIPH_ID_I2S1,        4,      12,     16},
-       {PERIPH_ID_SPI3,        0,      0,      4},
-       {PERIPH_ID_SPI4,        4,      12,     16},
-       {PERIPH_ID_SDMMC4,      16,     0,      8},
-       {PERIPH_ID_PWM0,        24,     0,      -1},
-       {PERIPH_ID_PWM1,        24,     0,      -1},
-       {PERIPH_ID_PWM2,        24,     0,      -1},
-       {PERIPH_ID_PWM3,        24,     0,      -1},
-       {PERIPH_ID_PWM4,        24,     0,      -1},
-
-       {PERIPH_ID_NONE,        -1,     -1,     -1},
+       /* periph id            s_mask  d_mask  p_mask  s_bit   d_bit   p_bit */
+       {PERIPH_ID_UART0,       0xf,    0xf,    -1,     0,      0,      -1},
+       {PERIPH_ID_UART1,       0xf,    0xf,    -1,     4,      4,      -1},
+       {PERIPH_ID_UART2,       0xf,    0xf,    -1,     8,      8,      -1},
+       {PERIPH_ID_UART3,       0xf,    0xf,    -1,     12,     12,     -1},
+       {PERIPH_ID_I2C0,        -1,     0x7,    0x7,    -1,     24,     0},
+       {PERIPH_ID_I2C1,        -1,     0x7,    0x7,    -1,     24,     0},
+       {PERIPH_ID_I2C2,        -1,     0x7,    0x7,    -1,     24,     0},
+       {PERIPH_ID_I2C3,        -1,     0x7,    0x7,    -1,     24,     0},
+       {PERIPH_ID_I2C4,        -1,     0x7,    0x7,    -1,     24,     0},
+       {PERIPH_ID_I2C5,        -1,     0x7,    0x7,    -1,     24,     0},
+       {PERIPH_ID_I2C6,        -1,     0x7,    0x7,    -1,     24,     0},
+       {PERIPH_ID_I2C7,        -1,     0x7,    0x7,    -1,     24,     0},
+       {PERIPH_ID_SPI0,        0xf,    0xf,    0xff,   16,     0,      8},
+       {PERIPH_ID_SPI1,        0xf,    0xf,    0xff,   20,     16,     24},
+       {PERIPH_ID_SPI2,        0xf,    0xf,    0xff,   24,     0,      8},
+       {PERIPH_ID_SDMMC0,      0xf,    0xf,    0xff,   0,      0,      8},
+       {PERIPH_ID_SDMMC1,      0xf,    0xf,    0xff,   4,      16,     24},
+       {PERIPH_ID_SDMMC2,      0xf,    0xf,    0xff,   8,      0,      8},
+       {PERIPH_ID_SDMMC3,      0xf,    0xf,    0xff,   12,     16,     24},
+       {PERIPH_ID_I2S0,        0xf,    0xf,    0xff,   0,      0,      4},
+       {PERIPH_ID_I2S1,        0xf,    0xf,    0xff,   4,      12,     16},
+       {PERIPH_ID_SPI3,        0xf,    0xf,    0xff,   0,      0,      4},
+       {PERIPH_ID_SPI4,        0xf,    0xf,    0xff,   4,      12,     16},
+       {PERIPH_ID_SDMMC4,      0xf,    0xf,    0xff,   16,     0,      8},
+       {PERIPH_ID_PWM0,        0xf,    0xf,    -1,     24,     0,      -1},
+       {PERIPH_ID_PWM1,        0xf,    0xf,    -1,     24,     0,      -1},
+       {PERIPH_ID_PWM2,        0xf,    0xf,    -1,     24,     0,      -1},
+       {PERIPH_ID_PWM3,        0xf,    0xf,    -1,     24,     0,      -1},
+       {PERIPH_ID_PWM4,        0xf,    0xf,    -1,     24,     0,      -1},
+
+       {PERIPH_ID_NONE,        -1,     -1,     -1,     -1,     -1,     -1},
 };
 
 static struct clk_bit_info exynos542x_bit_info[] = {
-       {PERIPH_ID_UART0,       4,      8,      -1},
-       {PERIPH_ID_UART1,       8,      12,     -1},
-       {PERIPH_ID_UART2,       12,     16,     -1},
-       {PERIPH_ID_UART3,       16,     20,     -1},
-       {PERIPH_ID_I2C0,        -1,     8,      -1},
-       {PERIPH_ID_I2C1,        -1,     8,      -1},
-       {PERIPH_ID_I2C2,        -1,     8,      -1},
-       {PERIPH_ID_I2C3,        -1,     8,      -1},
-       {PERIPH_ID_I2C4,        -1,     8,      -1},
-       {PERIPH_ID_I2C5,        -1,     8,      -1},
-       {PERIPH_ID_I2C6,        -1,     8,      -1},
-       {PERIPH_ID_I2C7,        -1,     8,      -1},
-       {PERIPH_ID_SPI0,        20,     20,     8},
-       {PERIPH_ID_SPI1,        24,     24,     16},
-       {PERIPH_ID_SPI2,        28,     28,     24},
-       {PERIPH_ID_SDMMC0,      8,      0,      -1},
-       {PERIPH_ID_SDMMC1,      12,     10,     -1},
-       {PERIPH_ID_SDMMC2,      16,     20,     -1},
-       {PERIPH_ID_I2C8,        -1,     8,      -1},
-       {PERIPH_ID_I2C9,        -1,     8,      -1},
-       {PERIPH_ID_I2S0,        0,      0,      4},
-       {PERIPH_ID_I2S1,        4,      12,     16},
-       {PERIPH_ID_SPI3,        12,     16,     0},
-       {PERIPH_ID_SPI4,        16,     20,     8},
-       {PERIPH_ID_PWM0,        24,     28,     -1},
-       {PERIPH_ID_PWM1,        24,     28,     -1},
-       {PERIPH_ID_PWM2,        24,     28,     -1},
-       {PERIPH_ID_PWM3,        24,     28,     -1},
-       {PERIPH_ID_PWM4,        24,     28,     -1},
-       {PERIPH_ID_I2C10,       -1,     8,      -1},
-
-       {PERIPH_ID_NONE,        -1,     -1,     -1},
+       /* periph id            s_mask  d_mask  p_mask  s_bit   d_bit   p_bit */
+       {PERIPH_ID_UART0,       0xf,    0xf,    -1,     4,      8,      -1},
+       {PERIPH_ID_UART1,       0xf,    0xf,    -1,     8,      12,     -1},
+       {PERIPH_ID_UART2,       0xf,    0xf,    -1,     12,     16,     -1},
+       {PERIPH_ID_UART3,       0xf,    0xf,    -1,     16,     20,     -1},
+       {PERIPH_ID_I2C0,        -1,     0x3f,   -1,     -1,     8,      -1},
+       {PERIPH_ID_I2C1,        -1,     0x3f,   -1,     -1,     8,      -1},
+       {PERIPH_ID_I2C2,        -1,     0x3f,   -1,     -1,     8,      -1},
+       {PERIPH_ID_I2C3,        -1,     0x3f,   -1,     -1,     8,      -1},
+       {PERIPH_ID_I2C4,        -1,     0x3f,   -1,     -1,     8,      -1},
+       {PERIPH_ID_I2C5,        -1,     0x3f,   -1,     -1,     8,      -1},
+       {PERIPH_ID_I2C6,        -1,     0x3f,   -1,     -1,     8,      -1},
+       {PERIPH_ID_I2C7,        -1,     0x3f,   -1,     -1,     8,      -1},
+       {PERIPH_ID_SPI0,        0xf,    0xf,    0xff,   20,     20,     8},
+       {PERIPH_ID_SPI1,        0xf,    0xf,    0xff,   24,     24,     16},
+       {PERIPH_ID_SPI2,        0xf,    0xf,    0xff,   28,     28,     24},
+       {PERIPH_ID_SDMMC0,      0x7,    0x3ff,  -1,     8,      0,      -1},
+       {PERIPH_ID_SDMMC1,      0x7,    0x3ff,  -1,     12,     10,     -1},
+       {PERIPH_ID_SDMMC2,      0x7,    0x3ff,  -1,     16,     20,     -1},
+       {PERIPH_ID_I2C8,        -1,     0x3f,   -1,     -1,     8,      -1},
+       {PERIPH_ID_I2C9,        -1,     0x3f,   -1,     -1,     8,      -1},
+       {PERIPH_ID_I2S0,        0xf,    0xf,    0xff,   0,      0,      4},
+       {PERIPH_ID_I2S1,        0xf,    0xf,    0xff,   4,      12,     16},
+       {PERIPH_ID_SPI3,        0xf,    0xf,    0xff,   12,     16,     0},
+       {PERIPH_ID_SPI4,        0xf,    0xf,    0xff,   16,     20,     8},
+       {PERIPH_ID_PWM0,        0xf,    0xf,    -1,     24,     28,     -1},
+       {PERIPH_ID_PWM1,        0xf,    0xf,    -1,     24,     28,     -1},
+       {PERIPH_ID_PWM2,        0xf,    0xf,    -1,     24,     28,     -1},
+       {PERIPH_ID_PWM3,        0xf,    0xf,    -1,     24,     28,     -1},
+       {PERIPH_ID_PWM4,        0xf,    0xf,    -1,     24,     28,     -1},
+       {PERIPH_ID_I2C10,       -1,     0x3f,   -1,     -1,     8,      -1},
+
+       {PERIPH_ID_NONE,        -1,     -1,     -1,     -1,     -1,     -1},
 };
 
 /* Epll Clock division values to achive different frequency output */
@@ -362,8 +365,8 @@ static struct clk_bit_info *get_clk_bit_info(int peripheral)
 static unsigned long exynos5_get_periph_rate(int peripheral)
 {
        struct clk_bit_info *bit_info = get_clk_bit_info(peripheral);
-       unsigned long sclk, sub_clk = 0;
-       unsigned int src, div, sub_div = 0;
+       unsigned long sclk = 0;
+       unsigned int src = 0, div = 0, sub_div = 0;
        struct exynos5_clock *clk =
                        (struct exynos5_clock *)samsung_get_base_clock();
 
@@ -385,30 +388,30 @@ static unsigned long exynos5_get_periph_rate(int peripheral)
                break;
        case PERIPH_ID_I2S0:
                src = readl(&clk->src_mau);
-               div = readl(&clk->div_mau);
+               div = sub_div = readl(&clk->div_mau);
        case PERIPH_ID_SPI0:
        case PERIPH_ID_SPI1:
                src = readl(&clk->src_peric1);
-               div = readl(&clk->div_peric1);
+               div = sub_div = readl(&clk->div_peric1);
                break;
        case PERIPH_ID_SPI2:
                src = readl(&clk->src_peric1);
-               div = readl(&clk->div_peric2);
+               div = sub_div = readl(&clk->div_peric2);
                break;
        case PERIPH_ID_SPI3:
        case PERIPH_ID_SPI4:
                src = readl(&clk->sclk_src_isp);
-               div = readl(&clk->sclk_div_isp);
+               div = sub_div = readl(&clk->sclk_div_isp);
                break;
        case PERIPH_ID_SDMMC0:
        case PERIPH_ID_SDMMC1:
                src = readl(&clk->src_fsys);
-               div = readl(&clk->div_fsys1);
+               div = sub_div = readl(&clk->div_fsys1);
                break;
        case PERIPH_ID_SDMMC2:
        case PERIPH_ID_SDMMC3:
                src = readl(&clk->src_fsys);
-               div = readl(&clk->div_fsys2);
+               div = sub_div = readl(&clk->div_fsys2);
                break;
        case PERIPH_ID_I2C0:
        case PERIPH_ID_I2C1:
@@ -418,19 +421,17 @@ static unsigned long exynos5_get_periph_rate(int peripheral)
        case PERIPH_ID_I2C5:
        case PERIPH_ID_I2C6:
        case PERIPH_ID_I2C7:
-               sclk = exynos5_get_pll_clk(MPLL);
-               sub_div = ((readl(&clk->div_top1) >> bit_info->div_bit)
-                                                               & 0x7) + 1;
-               div = ((readl(&clk->div_top0) >> bit_info->prediv_bit)
-                                                               & 0x7) + 1;
-               return (sclk / sub_div) / div;
+               src = EXYNOS_SRC_MPLL;
+               div = readl(&clk->div_top1);
+               sub_div = readl(&clk->div_top0);
+               break;
        default:
                debug("%s: invalid peripheral %d", __func__, peripheral);
                return -1;
        };
 
        if (bit_info->src_bit >= 0)
-               src = (src >> bit_info->src_bit) & 0xf;
+               src = (src >> bit_info->src_bit) & bit_info->src_mask;
 
        switch (src) {
        case EXYNOS_SRC_MPLL:
@@ -443,28 +444,28 @@ static unsigned long exynos5_get_periph_rate(int peripheral)
                sclk = exynos5_get_pll_clk(VPLL);
                break;
        default:
+               debug("%s: EXYNOS_SRC %d not supported\n", __func__, src);
                return 0;
        }
 
-       /* Ratio clock division for this peripheral */
-       if (bit_info->div_bit >= 0) {
-               sub_div = (div >> bit_info->div_bit) & 0xf;
-               sub_clk = sclk / (sub_div + 1);
-       }
+       /* Clock divider ratio for this peripheral */
+       if (bit_info->div_bit >= 0)
+               div = (div >> bit_info->div_bit) & bit_info->div_mask;
 
-       if (bit_info->prediv_bit >= 0) {
-               div = (div >> bit_info->prediv_bit) & 0xff;
-               return sub_clk / (div + 1);
-       }
+       /* Clock pre-divider ratio for this peripheral */
+       if (bit_info->prediv_bit >= 0)
+               sub_div = (sub_div >> bit_info->prediv_bit)
+                         & bit_info->prediv_mask;
 
-       return sub_clk;
+       /* Calculate and return required clock rate */
+       return (sclk / (div + 1)) / (sub_div + 1);
 }
 
 static unsigned long exynos542x_get_periph_rate(int peripheral)
 {
        struct clk_bit_info *bit_info = get_clk_bit_info(peripheral);
-       unsigned long sclk, sub_clk = 0;
-       unsigned int src, div, sub_div = 0;
+       unsigned long sclk = 0;
+       unsigned int src = 0, div = 0, sub_div = 0;
        struct exynos5420_clock *clk =
                        (struct exynos5420_clock *)samsung_get_base_clock();
 
@@ -512,17 +513,16 @@ static unsigned long exynos542x_get_periph_rate(int peripheral)
        case PERIPH_ID_I2C8:
        case PERIPH_ID_I2C9:
        case PERIPH_ID_I2C10:
-               sclk = exynos542x_get_pll_clk(MPLL);
-               sub_div = ((readl(&clk->div_top1) >> bit_info->div_bit)
-                                                               & 0x7) + 1;
-               return sclk / sub_div;
+               src = EXYNOS542X_SRC_MPLL;
+               div = readl(&clk->div_top1);
+               break;
        default:
                debug("%s: invalid peripheral %d", __func__, peripheral);
                return -1;
        };
 
        if (bit_info->src_bit >= 0)
-               src = (src >> bit_info->src_bit) & 0xf;
+               src = (src >> bit_info->src_bit) & bit_info->src_mask;
 
        switch (src) {
        case EXYNOS542X_SRC_MPLL:
@@ -538,21 +538,21 @@ static unsigned long exynos542x_get_periph_rate(int peripheral)
                sclk = exynos542x_get_pll_clk(RPLL);
                break;
        default:
+               debug("%s: EXYNOS542X_SRC %d not supported", __func__, src);
                return 0;
        }
 
-       /* Ratio clock division for this peripheral */
-       if (bit_info->div_bit >= 0) {
-               div = (div >> bit_info->div_bit) & 0xf;
-               sub_clk = sclk / (div + 1);
-       }
+       /* Clock divider ratio for this peripheral */
+       if (bit_info->div_bit >= 0)
+               div = (div >> bit_info->div_bit) & bit_info->div_mask;
 
-       if (bit_info->prediv_bit >= 0) {
-               sub_div = (sub_div >> bit_info->prediv_bit) & 0xff;
-               return sub_clk / (sub_div + 1);
-       }
+       /* Clock pre-divider ratio for this peripheral */
+       if (bit_info->prediv_bit >= 0)
+               sub_div = (sub_div >> bit_info->prediv_bit)
+                         & bit_info->prediv_mask;
 
-       return sub_clk;
+       /* Calculate and return required clock rate */
+       return (sclk / (div + 1)) / (sub_div + 1);
 }
 
 unsigned long clock_get_periph_rate(int peripheral)
@@ -1027,6 +1027,40 @@ static unsigned long exynos5420_get_lcd_clk(void)
        return pclk;
 }
 
+static unsigned long exynos5800_get_lcd_clk(void)
+{
+       struct exynos5420_clock *clk =
+               (struct exynos5420_clock *)samsung_get_base_clock();
+       unsigned long sclk;
+       unsigned int sel;
+       unsigned int ratio;
+
+       /*
+        * CLK_SRC_DISP10
+        * CLKMUX_FIMD1 [6:4]
+        */
+       sel = (readl(&clk->src_disp10) >> 4) & 0x7;
+
+       if (sel) {
+               /*
+                * Mapping of CLK_SRC_DISP10 CLKMUX_FIMD1 [6:4] values into
+                * PLLs. The first element is a placeholder to bypass the
+                * default settig.
+                */
+               const int reg_map[] = {0, CPLL, DPLL, MPLL, SPLL, IPLL, EPLL,
+                                                                       RPLL};
+               sclk = get_pll_clk(reg_map[sel]);
+       } else
+               sclk = CONFIG_SYS_CLK_FREQ;
+       /*
+        * CLK_DIV_DISP10
+        * FIMD1_RATIO [3:0]
+        */
+       ratio = readl(&clk->div_disp10) & 0xf;
+
+       return sclk / (ratio + 1);
+}
+
 void exynos4_set_lcd_clk(void)
 {
        struct exynos4_clock *clk =
@@ -1158,6 +1192,28 @@ void exynos5420_set_lcd_clk(void)
        writel(cfg, &clk->div_disp10);
 }
 
+void exynos5800_set_lcd_clk(void)
+{
+       struct exynos5420_clock *clk =
+               (struct exynos5420_clock *)samsung_get_base_clock();
+       unsigned int cfg;
+
+       /*
+        * Use RPLL for pixel clock
+        * CLK_SRC_DISP10 CLKMUX_FIMD1 [6:4]
+        * ==================
+        * 111: SCLK_RPLL
+        */
+       cfg = readl(&clk->src_disp10) | (0x7 << 4);
+       writel(cfg, &clk->src_disp10);
+
+       /*
+        * CLK_DIV_DISP10
+        * FIMD1_RATIO          [3:0]
+        */
+       clrsetbits_le32(&clk->div_disp10, 0xf << 0, 0x0 << 0);
+}
+
 void exynos4_set_mipi_clk(void)
 {
        struct exynos4_clock *clk =
@@ -1645,8 +1701,10 @@ unsigned long get_lcd_clk(void)
        if (cpu_is_exynos4())
                return exynos4_get_lcd_clk();
        else {
-               if (proid_is_exynos5420() || proid_is_exynos5800())
+               if (proid_is_exynos5420())
                        return exynos5420_get_lcd_clk();
+               else if (proid_is_exynos5800())
+                       return exynos5800_get_lcd_clk();
                else
                        return exynos5_get_lcd_clk();
        }
@@ -1659,8 +1717,10 @@ void set_lcd_clk(void)
        else {
                if (proid_is_exynos5250())
                        exynos5_set_lcd_clk();
-               else if (proid_is_exynos5420() || proid_is_exynos5800())
+               else if (proid_is_exynos5420())
                        exynos5420_set_lcd_clk();
+               else
+                       exynos5800_set_lcd_clk();
        }
 }