]> git.sur5r.net Git - u-boot/blobdiff - arch/arm/cpu/armv7/exynos/clock_init_exynos5.c
Exynos542x: cache: Disable clean/evict push to external
[u-boot] / arch / arm / cpu / armv7 / exynos / clock_init_exynos5.c
index 1d6977fa43727a1f342b9433496a5e029508d35b..0aff3d0d0cf454c25f8e90d8d6f1080dbf3da4c7 100644 (file)
@@ -179,6 +179,10 @@ struct mem_timings mem_timings[] = {
                .spll_mdiv = 0xc8,
                .spll_pdiv = 0x3,
                .spll_sdiv = 0x2,
+               /* RPLL @70.5Mhz */
+               .rpll_mdiv = 0x5E,
+               .rpll_pdiv = 0x2,
+               .rpll_sdiv = 0x4,
 
                .direct_cmd_msr = {
                        0x00020018, 0x00030000, 0x00010046, 0x00000d70,
@@ -800,6 +804,7 @@ static void exynos5420_system_clock_init(void)
        writel(mem->ipll_pdiv * PLL_LOCK_FACTOR, &clk->ipll_lock);
        writel(mem->spll_pdiv * PLL_LOCK_FACTOR, &clk->spll_lock);
        writel(mem->kpll_pdiv * PLL_LOCK_FACTOR, &clk->kpll_lock);
+       writel(mem->rpll_pdiv * PLL_X_LOCK_FACTOR, &clk->rpll_lock);
 
        setbits_le32(&clk->src_cpu, MUX_HPM_SEL_MASK);
 
@@ -898,6 +903,14 @@ static void exynos5420_system_clock_init(void)
        while ((readl(&clk->spll_con0) & PLL_LOCKED) == 0)
                ;
 
+       /* Set RPLL */
+       writel(RPLL_CON2_VAL, &clk->rpll_con2);
+       writel(RPLL_CON1_VAL, &clk->rpll_con1);
+       val = set_pll(mem->rpll_mdiv, mem->rpll_pdiv, mem->rpll_sdiv);
+       writel(val, &clk->rpll_con0);
+       while ((readl(&clk->rpll_con0) & PLL_LOCKED) == 0)
+               ;
+
        writel(CLK_DIV_CDREX0_VAL, &clk->div_cdrex0);
        writel(CLK_DIV_CDREX1_VAL, &clk->div_cdrex1);
 
@@ -958,7 +971,7 @@ static void exynos5420_system_clock_init(void)
 
 void system_clock_init(void)
 {
-       if (proid_is_exynos5420())
+       if (proid_is_exynos5420() || proid_is_exynos5800())
                exynos5420_system_clock_init();
        else
                exynos5250_system_clock_init();