#define CLK_DIV_CPERI1_VAL NOT_AVAILABLE
#else
+
+#define CPU_CONFIG_STATUS_OFFSET 0x80
+#define CPU_RST_FLAG_VAL 0xFCBA0D10
#define PAD_RETENTION_DRAM_COREBLK_VAL 0x10000000
/* APLL_CON1 */
#define CLK_SRC_TOP2_VAL 0x11101000
#define CLK_SRC_TOP3_VAL 0x11111111
#define CLK_SRC_TOP4_VAL 0x11110111
-#define CLK_SRC_TOP5_VAL 0x11111100
+#define CLK_SRC_TOP5_VAL 0x11111101
#define CLK_SRC_TOP6_VAL 0x11110111
#define CLK_SRC_TOP7_VAL 0x00022200