*/
#include <common.h>
+#include <fdtdec.h>
#include <asm/arch/gpio.h>
#include <asm/arch/pinmux.h>
#include <asm/arch/sromc.h>
return 0;
}
+static void exynos4_i2c_config(int peripheral, int flags)
+{
+ struct exynos4_gpio_part1 *gpio1 =
+ (struct exynos4_gpio_part1 *) samsung_get_base_gpio_part1();
+
+ switch (peripheral) {
+ case PERIPH_ID_I2C0:
+ s5p_gpio_cfg_pin(&gpio1->d1, 0, GPIO_FUNC(0x2));
+ s5p_gpio_cfg_pin(&gpio1->d1, 1, GPIO_FUNC(0x2));
+ break;
+ case PERIPH_ID_I2C1:
+ s5p_gpio_cfg_pin(&gpio1->d1, 2, GPIO_FUNC(0x2));
+ s5p_gpio_cfg_pin(&gpio1->d1, 3, GPIO_FUNC(0x2));
+ break;
+ case PERIPH_ID_I2C2:
+ s5p_gpio_cfg_pin(&gpio1->a0, 6, GPIO_FUNC(0x3));
+ s5p_gpio_cfg_pin(&gpio1->a0, 7, GPIO_FUNC(0x3));
+ break;
+ case PERIPH_ID_I2C3:
+ s5p_gpio_cfg_pin(&gpio1->a1, 2, GPIO_FUNC(0x3));
+ s5p_gpio_cfg_pin(&gpio1->a1, 3, GPIO_FUNC(0x3));
+ break;
+ case PERIPH_ID_I2C4:
+ s5p_gpio_cfg_pin(&gpio1->b, 2, GPIO_FUNC(0x3));
+ s5p_gpio_cfg_pin(&gpio1->b, 3, GPIO_FUNC(0x3));
+ break;
+ case PERIPH_ID_I2C5:
+ s5p_gpio_cfg_pin(&gpio1->b, 6, GPIO_FUNC(0x3));
+ s5p_gpio_cfg_pin(&gpio1->b, 7, GPIO_FUNC(0x3));
+ break;
+ case PERIPH_ID_I2C6:
+ s5p_gpio_cfg_pin(&gpio1->c1, 3, GPIO_FUNC(0x4));
+ s5p_gpio_cfg_pin(&gpio1->c1, 4, GPIO_FUNC(0x4));
+ break;
+ case PERIPH_ID_I2C7:
+ s5p_gpio_cfg_pin(&gpio1->d0, 2, GPIO_FUNC(0x3));
+ s5p_gpio_cfg_pin(&gpio1->d0, 3, GPIO_FUNC(0x3));
+ break;
+ }
+}
+
static int exynos4_mmc_config(int peripheral, int flags)
{
struct exynos4_gpio_part2 *gpio2 =
return 0;
}
-static int exynos4_pinmux_config(int peripheral, int flags)
-{
- switch (peripheral) {
- case PERIPH_ID_SDMMC0:
- case PERIPH_ID_SDMMC2:
- return exynos4_mmc_config(peripheral, flags);
- case PERIPH_ID_SDMMC1:
- case PERIPH_ID_SDMMC3:
- case PERIPH_ID_SDMMC4:
- printf("SDMMC device %d not implemented\n", peripheral);
- return -1;
- default:
- debug("%s: invalid peripheral %d", __func__, peripheral);
- return -1;
- }
-
- return 0;
-}
-
-static void exynos4_i2c_config(int peripheral, int flags)
+static void exynos4_uart_config(int peripheral)
{
struct exynos4_gpio_part1 *gpio1 =
- (struct exynos4_gpio_part1 *) samsung_get_base_gpio_part1();
+ (struct exynos4_gpio_part1 *)samsung_get_base_gpio_part1();
+ struct s5p_gpio_bank *bank;
+ int i, start, count;
switch (peripheral) {
- case PERIPH_ID_I2C0:
- s5p_gpio_cfg_pin(&gpio1->d1, 0, GPIO_FUNC(0x2));
- s5p_gpio_cfg_pin(&gpio1->d1, 1, GPIO_FUNC(0x2));
- break;
- case PERIPH_ID_I2C1:
- s5p_gpio_cfg_pin(&gpio1->d1, 2, GPIO_FUNC(0x2));
- s5p_gpio_cfg_pin(&gpio1->d1, 3, GPIO_FUNC(0x2));
- break;
- case PERIPH_ID_I2C2:
- s5p_gpio_cfg_pin(&gpio1->a0, 6, GPIO_FUNC(0x3));
- s5p_gpio_cfg_pin(&gpio1->a0, 7, GPIO_FUNC(0x3));
- break;
- case PERIPH_ID_I2C3:
- s5p_gpio_cfg_pin(&gpio1->a1, 2, GPIO_FUNC(0x3));
- s5p_gpio_cfg_pin(&gpio1->a1, 3, GPIO_FUNC(0x3));
- break;
- case PERIPH_ID_I2C4:
- s5p_gpio_cfg_pin(&gpio1->b, 2, GPIO_FUNC(0x3));
- s5p_gpio_cfg_pin(&gpio1->b, 3, GPIO_FUNC(0x3));
+ case PERIPH_ID_UART0:
+ bank = &gpio1->a0;
+ start = 0;
+ count = 4;
break;
- case PERIPH_ID_I2C5:
- s5p_gpio_cfg_pin(&gpio1->b, 6, GPIO_FUNC(0x3));
- s5p_gpio_cfg_pin(&gpio1->b, 7, GPIO_FUNC(0x3));
+ case PERIPH_ID_UART1:
+ bank = &gpio1->a0;
+ start = 4;
+ count = 4;
break;
- case PERIPH_ID_I2C6:
- s5p_gpio_cfg_pin(&gpio1->c1, 3, GPIO_FUNC(0x4));
- s5p_gpio_cfg_pin(&gpio1->c1, 4, GPIO_FUNC(0x4));
+ case PERIPH_ID_UART2:
+ bank = &gpio1->a1;
+ start = 0;
+ count = 4;
break;
- case PERIPH_ID_I2C7:
- s5p_gpio_cfg_pin(&gpio1->d0, 2, GPIO_FUNC(0x3));
- s5p_gpio_cfg_pin(&gpio1->d0, 3, GPIO_FUNC(0x3));
+ case PERIPH_ID_UART3:
+ bank = &gpio1->a1;
+ start = 4;
+ count = 2;
break;
}
+ for (i = start; i < start + count; i++) {
+ s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE);
+ s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
+ }
}
-
static int exynos4_pinmux_config(int peripheral, int flags)
{
switch (peripheral) {
+ case PERIPH_ID_UART0:
+ case PERIPH_ID_UART1:
+ case PERIPH_ID_UART2:
+ case PERIPH_ID_UART3:
+ exynos4_uart_config(peripheral);
+ break;
case PERIPH_ID_I2C0:
case PERIPH_ID_I2C1:
case PERIPH_ID_I2C2:
case PERIPH_ID_I2C7:
exynos4_i2c_config(peripheral, flags);
break;
+ case PERIPH_ID_SDMMC0:
+ case PERIPH_ID_SDMMC2:
+ return exynos4_mmc_config(peripheral, flags);
+ case PERIPH_ID_SDMMC1:
+ case PERIPH_ID_SDMMC3:
+ case PERIPH_ID_SDMMC4:
+ printf("SDMMC device %d not implemented\n", peripheral);
+ return -1;
default:
debug("%s: invalid peripheral %d", __func__, peripheral);
return -1;
return -1;
}
}
+
+#ifdef CONFIG_OF_CONTROL
+static int exynos5_pinmux_decode_periph_id(const void *blob, int node)
+{
+ int err;
+ u32 cell[3];
+
+ err = fdtdec_get_int_array(blob, node, "interrupts", cell,
+ ARRAY_SIZE(cell));
+ if (err)
+ return PERIPH_ID_NONE;
+
+ /* check for invalid peripheral id */
+ if ((PERIPH_ID_SDMMC4 > cell[1]) || (cell[1] < PERIPH_ID_UART0))
+ return cell[1];
+
+ debug(" invalid peripheral id\n");
+ return PERIPH_ID_NONE;
+}
+
+int pinmux_decode_periph_id(const void *blob, int node)
+{
+ if (cpu_is_exynos5())
+ return exynos5_pinmux_decode_periph_id(blob, node);
+ else
+ return PERIPH_ID_NONE;
+}
+#endif