Merge branch 'buildman' of git://git.denx.de/u-boot-x86

[u-boot] / arch / arm / cpu / armv7 / exynos / system.c

diff --git a/arch/arm/cpu/armv7/exynos/system.c b/arch/arm/cpu/armv7/exynos/system.c
index cc6ee031c7384b121f21e223ca3435b2e8fd6232..ad12445832cf7415e52e8593b595ab33a0b4d375 100644 (file)
--- a/arch/arm/cpu/armv7/exynos/system.c
+++ b/arch/arm/cpu/armv7/exynos/system.c
@@ -2,23 +2,7 @@
  * Copyright (C) 2012 Samsung Electronics
  * Donghwa Lee <dh09.lee@samsung.com>
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #include <common.h>
@@ -29,7 +13,6 @@ static void exynos5_set_usbhost_mode(unsigned int mode)
 {
        struct exynos5_sysreg *sysreg =
                (struct exynos5_sysreg *)samsung_get_base_sysreg();
-       unsigned int phy_cfg;
 
        /* Setting USB20PHY_CONFIG register to USB 2.0 HOST link */
        if (mode == USB20_PHY_CFG_HOST_LINK_EN) {
@@ -63,8 +46,26 @@ static void exynos4_set_system_display(void)
        writel(cfg, &sysreg->display_ctrl);
 }
 
+static void exynos5_set_system_display(void)
+{
+       struct exynos5_sysreg *sysreg =
+           (struct exynos5_sysreg *)samsung_get_base_sysreg();
+       unsigned int cfg = 0;
+
+       /*
+        * system register path set
+        * 0: MIE/MDNIE
+        * 1: FIMD Bypass
+        */
+       cfg = readl(&sysreg->disp1blk_cfg);
+       cfg |= (1 << 15);
+       writel(cfg, &sysreg->disp1blk_cfg);
+}
+
 void set_system_display_ctrl(void)
 {
        if (cpu_is_exynos4())
                exynos4_set_system_display();
+       else
+               exynos5_set_system_display();
 }