Merge git://git.denx.de/u-boot-fsl-qoriq

[u-boot] / arch / arm / cpu / armv7 / ls102xa / Kconfig

diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig b/arch/arm/cpu/armv7/ls102xa/Kconfig
index f94568a2e4f704800314d2edd4f47b0adf5482f2..b61f3cdcded1ece1b8a8af7b5973fb79dc674cc6 100644 (file)
--- a/arch/arm/cpu/armv7/ls102xa/Kconfig
+++ b/arch/arm/cpu/armv7/ls102xa/Kconfig
@@ -1,14 +1,31 @@
 config ARCH_LS1021A
        bool
+       select SYS_FSL_ERRATUM_A008378
+       select SYS_FSL_ERRATUM_A008407
+       select SYS_FSL_ERRATUM_A009663
+       select SYS_FSL_ERRATUM_A009942
        select SYS_FSL_ERRATUM_A010315
        select SYS_FSL_SRDS_1
        select SYS_HAS_SERDES
-       select SYS_FSL_DDR_BE
-       select SYS_FSL_DDR_VER_50
+       select SYS_FSL_DDR_BE if SYS_FSL_DDR
+       select SYS_FSL_DDR_VER_50 if SYS_FSL_DDR
+       select SYS_FSL_HAS_DDR3 if SYS_FSL_DDR
+       select SYS_FSL_HAS_DDR4 if SYS_FSL_DDR
+       select SYS_FSL_HAS_SEC
+       select SYS_FSL_SEC_COMPAT_5
+       select SYS_FSL_SEC_LE
 
 menu "LS102xA architecture"
        depends on ARCH_LS1021A
 
+config FSL_PCIE_COMPAT
+       string "PCIe compatible of Kernel DT"
+       depends on PCIE_LAYERSCAPE
+       default "fsl,ls1021a-pcie" if ARCH_LS1021A
+       help
+         This compatible is used to find pci controller node in Kernel DT
+         to complete fixup.
+
 config LS1_DEEP_SLEEP
        bool "Deep sleep"
        depends on ARCH_LS1021A
@@ -24,10 +41,6 @@ config MAX_CPUS
          cores, count the reserved ports. This will allocate enough memory
          in spin table to properly handle all cores.
 
-config NUM_DDR_CONTROLLERS
-       int "Maximum DDR controllers"
-       default 1
-
 config SECURE_BOOT
        bool    "Secure Boot"
        help
@@ -46,50 +59,12 @@ config SYS_FSL_SRDS_2
 config SYS_HAS_SERDES
        bool
 
-config SYS_FSL_DDR
-       bool "Freescale DDR driver"
-       help
-         Select Freescale General DDR driver, shared between most Freescale
-         PowerPC- based SoCs (such as mpc83xx, mpc85xx, mpc86xx) and ARM-
-         based Layerscape SoCs (such as ls2080a).
-
-config SYS_FSL_DDR_BE
-       bool
-       default y
-       help
-         Access DDR registers in big-endian.
-
-config SYS_FSL_DDR_VER
-       int
-       default 50 if SYS_FSL_DDR_VER_50
-
-config SYS_FSL_DDR_VER_50
-       bool
-
-config SYS_FSL_DDRC_ARM_GEN3
-       bool
-
-config SYS_FSL_DDRC_GEN4
-       bool
-
-config SYS_FSL_DDR3
-       bool "Freescale DDR3 controller"
-       depends on !SYS_FSL_DDR4
-       select SYS_FSL_DDR
-       select SYS_FSL_DDRC_ARM_GEN3
-       help
-         Enable Freescale DDR3 controller on ARM-based SoCs.
-
-config SYS_FSL_DDR4
-       bool "Freescale DDR4 controller"
-       select SYS_FSL_DDR
-       select SYS_FSL_DDRC_GEN4
-       help
-         Enable Freescale DDR4 controller.
-
 config SYS_FSL_IFC_BANK_COUNT
        int "Maximum banks of Integrated flash controller"
        depends on ARCH_LS1021A
        default 8
 
+config SYS_FSL_ERRATUM_A008407
+       bool
+
 endmenu