Merge branch 'master' of git://git.denx.de/u-boot-video

[u-boot] / arch / arm / cpu / armv7 / ls102xa / cpu.c

diff --git a/arch/arm/cpu/armv7/ls102xa/cpu.c b/arch/arm/cpu/armv7/ls102xa/cpu.c
index 18665a32d238a25a2387ba87179ded47ffac0df0..2f0df65582893356117c13841f593ccdefc8021d 100644 (file)
--- a/arch/arm/cpu/armv7/ls102xa/cpu.c
+++ b/arch/arm/cpu/armv7/ls102xa/cpu.c
@@ -13,9 +13,18 @@
 #include <tsec.h>
 #include <netdev.h>
 #include <fsl_esdhc.h>
+#include <config.h>
+#include <fsl_wdog.h>
 
 #include "fsl_epu.h"
 
+#define DCSR_RCPM2_BLOCK_OFFSET        0x223000
+#define DCSR_RCPM2_CPMFSMCR0   0x400
+#define DCSR_RCPM2_CPMFSMSR0   0x404
+#define DCSR_RCPM2_CPMFSMCR1   0x414
+#define DCSR_RCPM2_CPMFSMSR1   0x418
+#define CPMFSMSR_FSM_STATE_MASK        0x7f
+
 DECLARE_GLOBAL_DATA_PTR;
 
 #ifndef CONFIG_SYS_DCACHE_OFF
@@ -209,6 +218,14 @@ void enable_caches(void)
 }
 #endif /* #ifndef CONFIG_SYS_DCACHE_OFF */
 
+
+uint get_svr(void)
+{
+       struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+
+       return in_be32(&gur->svr);
+}
+
 #if defined(CONFIG_DISPLAY_CPUINFO)
 int print_cpuinfo(void)
 {
@@ -290,6 +307,28 @@ int cpu_eth_init(bd_t *bis)
 int arch_cpu_init(void)
 {
        void *epu_base = (void *)(CONFIG_SYS_DCSRBAR + EPU_BLOCK_OFFSET);
+       void *rcpm2_base =
+               (void *)(CONFIG_SYS_DCSRBAR + DCSR_RCPM2_BLOCK_OFFSET);
+       struct ccsr_scfg *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
+       u32 state;
+
+       /*
+        * The RCPM FSM state may not be reset after power-on.
+        * So, reset them.
+        */
+       state = in_be32(rcpm2_base + DCSR_RCPM2_CPMFSMSR0) &
+               CPMFSMSR_FSM_STATE_MASK;
+       if (state != 0) {
+               out_be32(rcpm2_base + DCSR_RCPM2_CPMFSMCR0, 0x80);
+               out_be32(rcpm2_base + DCSR_RCPM2_CPMFSMCR0, 0x0);
+       }
+
+       state = in_be32(rcpm2_base + DCSR_RCPM2_CPMFSMSR1) &
+               CPMFSMSR_FSM_STATE_MASK;
+       if (state != 0) {
+               out_be32(rcpm2_base + DCSR_RCPM2_CPMFSMCR1, 0x80);
+               out_be32(rcpm2_base + DCSR_RCPM2_CPMFSMCR1, 0x0);
+       }
 
        /*
         * After wakeup from deep sleep, Clear EPU registers
@@ -298,10 +337,12 @@ int arch_cpu_init(void)
         */
        fsl_epu_clean(epu_base);
 
+       setbits_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SEC_RD_WR);
+
        return 0;
 }
 
-#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT)
+#ifdef CONFIG_ARMV7_NONSEC
 /* Set the address at which the secondary core starts from.*/
 void smp_set_core_boot_addr(unsigned long addr, int corenr)
 {
@@ -316,5 +357,36 @@ void smp_kick_all_cpus(void)
        struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 
        out_be32(&gur->brrl, 0x2);
+
+       /*
+        * LS1 STANDBYWFE is not captured outside the ARM module in the soc.
+        * So add a delay to wait bootrom execute WFE.
+        */
+       udelay(1);
+
+       asm volatile("sev");
 }
 #endif
+
+void reset_cpu(ulong addr)
+{
+       struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR;
+
+       clrbits_be16(&wdog->wcr, WCR_SRS);
+
+       while (1) {
+               /*
+                * Let the watchdog trigger
+                */
+       }
+}
+
+void arch_preboot_os(void)
+{
+       unsigned long ctrl;
+
+       /* Disable PL1 Physical Timer */
+       asm("mrc p15, 0, %0, c14, c2, 1" : "=r" (ctrl));
+       ctrl &= ~ARCH_TIMER_CTRL_ENABLE;
+       asm("mcr p15, 0, %0, c14, c2, 1" : : "r" (ctrl));
+}