Merge branch 'master' of git://git.denx.de/u-boot-arm

[u-boot] / arch / arm / cpu / armv7 / mx5 / clock.c

diff --git a/arch/arm/cpu/armv7/mx5/clock.c b/arch/arm/cpu/armv7/mx5/clock.c
index a59b88a490b74009720c2bc91881317432b01448..76c2c529a88fb72e7a5f96e9497725b48e1f6646 100644 (file)
--- a/arch/arm/cpu/armv7/mx5/clock.c
+++ b/arch/arm/cpu/armv7/mx5/clock.c
@@ -111,12 +111,16 @@ void enable_usboh3_clk(unsigned char enable)
 }
 
 #ifdef CONFIG_I2C_MXC
-/* i2c_num can be from 0 - 2 */
+/* i2c_num can be from 0, to 1 for i.MX51 and 2 for i.MX53 */
 int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
 {
        u32 mask;
 
+#if defined(CONFIG_MX51)
+       if (i2c_num > 1)
+#elif defined(CONFIG_MX53)
        if (i2c_num > 2)
+#endif
                return -EINVAL;
        mask = MXC_CCM_CCGR_CG_MASK <<
                        (MXC_CCM_CCGR1_I2C1_OFFSET + (i2c_num << 1));
@@ -334,7 +338,7 @@ static u32 get_ipg_per_clk(void)
 /* Get the output clock rate of a standard PLL MUX for peripherals. */
 static u32 get_standard_pll_sel_clk(u32 clk_sel)
 {
-       u32 freq;
+       u32 freq = 0;
 
        switch (clk_sel & 0x3) {
        case 0:
@@ -390,6 +394,44 @@ static u32 imx_get_cspiclk(void)
        return ret_val;
 }
 
+/*
+ * get esdhc clock rate.
+ */
+static u32 get_esdhc_clk(u32 port)
+{
+       u32 clk_sel = 0, pred = 0, podf = 0, freq = 0;
+       u32 cscmr1 = readl(&mxc_ccm->cscmr1);
+       u32 cscdr1 = readl(&mxc_ccm->cscdr1);
+
+       switch (port) {
+       case 0:
+               clk_sel = MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_RD(cscmr1);
+               pred = MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_RD(cscdr1);
+               podf = MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_RD(cscdr1);
+               break;
+       case 1:
+               clk_sel = MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_RD(cscmr1);
+               pred = MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_RD(cscdr1);
+               podf = MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_RD(cscdr1);
+               break;
+       case 2:
+               if (cscmr1 & MXC_CCM_CSCMR1_ESDHC3_CLK_SEL)
+                       return get_esdhc_clk(1);
+               else
+                       return get_esdhc_clk(0);
+       case 3:
+               if (cscmr1 & MXC_CCM_CSCMR1_ESDHC4_CLK_SEL)
+                       return get_esdhc_clk(1);
+               else
+                       return get_esdhc_clk(0);
+       default:
+               break;
+       }
+
+       freq = get_standard_pll_sel_clk(clk_sel) / ((pred + 1) * (podf + 1));
+       return freq;
+}
+
 static u32 get_axi_a_clk(void)
 {
        u32 cbcdr = readl(&mxc_ccm->cbcdr);
@@ -473,6 +515,14 @@ unsigned int mxc_get_clock(enum mxc_clock clk)
                return get_uart_clk();
        case MXC_CSPI_CLK:
                return imx_get_cspiclk();
+       case MXC_ESDHC_CLK:
+               return get_esdhc_clk(0);
+       case MXC_ESDHC2_CLK:
+               return get_esdhc_clk(1);
+       case MXC_ESDHC3_CLK:
+               return get_esdhc_clk(2);
+       case MXC_ESDHC4_CLK:
+               return get_esdhc_clk(3);
        case MXC_FEC_CLK:
                return get_ipg_clk();
        case MXC_SATA_CLK:
@@ -878,7 +928,9 @@ int do_mx5_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
        printf("IPG        %8d kHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000);
        printf("IPG PERCLK %8d kHz\n", mxc_get_clock(MXC_IPG_PERCLK) / 1000);
        printf("DDR        %8d kHz\n", mxc_get_clock(MXC_DDR_CLK) / 1000);
-
+#ifdef CONFIG_MXC_SPI
+       printf("CSPI       %8d kHz\n", mxc_get_clock(MXC_CSPI_CLK) / 1000);
+#endif
        return 0;
 }