Merge git://git.denx.de/u-boot-fsl-qoriq

[u-boot] / arch / arm / cpu / armv7 / mx5 / lowlevel_init.S

diff --git a/arch/arm/cpu/armv7/mx5/lowlevel_init.S b/arch/arm/cpu/armv7/mx5/lowlevel_init.S
index d0bab4545a2d16763a7d96e17149b69f3e2913dd..f5bc6728b7c2ce4cbe4bcbdef260b39d1cfc1e32 100644 (file)
--- a/arch/arm/cpu/armv7/mx5/lowlevel_init.S
+++ b/arch/arm/cpu/armv7/mx5/lowlevel_init.S
@@ -3,20 +3,7 @@
  *
  * (C) Copyright 2009 Freescale Semiconductor, Inc.
  *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #include <config.h>
@@ -26,6 +13,13 @@
 
 .section ".text.init", "x"
 
+.macro init_arm_erratum
+       /* ARM erratum ID #468414 */
+       mrc 15, 0, r1, c1, c0, 1
+       orr r1, r1, #(1 << 5)    /* enable L1NEON bit */
+       mcr 15, 0, r1, c1, c0, 1
+.endm
+
 /*
  * L2CC Cache setup/invalidation/disable
  */
@@ -37,10 +31,10 @@
 
        /* reconfigure L2 cache aux control reg */
        ldr r0, =0xC0 |                 /* tag RAM */ \
-                0x4 |                  /* data RAM */ \
-                1 << 24 |              /* disable write allocate delay */ \
-                1 << 23 |              /* disable write allocate combine */ \
-                1 << 22                /* disable write allocate */
+                0x4 |                  /* data RAM */ \
+                1 << 24 |              /* disable write allocate delay */ \
+                1 << 23 |              /* disable write allocate combine */ \
+                1 << 22                /* disable write allocate */
 
 #if defined(CONFIG_MX51)
        ldr r3, [r4, #ROM_SI_REV]
@@ -51,6 +45,12 @@
 #endif
 
        mcr 15, 1, r0, c9, c0, 2
+
+       /* enable L2 cache */
+       mrc 15, 0, r0, c1, c0, 1
+       orr r0, r0, #2
+       mcr 15, 0, r0, c1, c0, 1
+
 .endm /* init_l2cc */
 
 /* AIPS setup - Only setup MPROTx registers.
@@ -296,20 +296,62 @@ setup_pll_func:
 
        setup_pll PLL1_BASE_ADDR, 800
 
+       setup_pll PLL3_BASE_ADDR, 400
+
+       /* Switch peripheral to PLL3 */
+       ldr r0, =CCM_BASE_ADDR
+       ldr r1, =0x00015154
+       str r1, [r0, #CLKCTL_CBCMR]
+       ldr r1, =0x02898945
+       str r1, [r0, #CLKCTL_CBCDR]
+       /* make sure change is effective */
+1:      ldr r1, [r0, #CLKCTL_CDHIPR]
+       cmp r1, #0x0
+       bne 1b
+
+       setup_pll PLL2_BASE_ADDR, 400
+
+       /* Switch peripheral to PLL2 */
+       ldr r0, =CCM_BASE_ADDR
+       ldr r1, =0x00888945
+       str r1, [r0, #CLKCTL_CBCDR]
+
+       ldr r1, =0x00016154
+       str r1, [r0, #CLKCTL_CBCMR]
+
+       /*change uart clk parent to pll2*/
+       ldr r1, [r0, #CLKCTL_CSCMR1]
+       and r1, r1, #0xfcffffff
+       orr r1, r1, #0x01000000
+       str r1, [r0, #CLKCTL_CSCMR1]
+
+       /* make sure change is effective */
+1:      ldr r1, [r0, #CLKCTL_CDHIPR]
+       cmp r1, #0x0
+       bne 1b
+
        setup_pll PLL3_BASE_ADDR, 216
 
+       setup_pll PLL4_BASE_ADDR, 455
+
        /* Set the platform clock dividers */
        ldr r0, =ARM_BASE_ADDR
-       ldr r1, =0x00000725
+       ldr r1, =0x00000124
        str r1, [r0, #0x14]
 
        ldr r0, =CCM_BASE_ADDR
-
        mov r1, #0
        str r1, [r0, #CLKCTL_CACRR]
 
-       /* Switch ARM back to PLL 1 */
-       str r4, [r0, #CLKCTL_CCSR]
+       /* Switch ARM back to PLL 1. */
+       mov r1, #0x0
+       str r1, [r0, #CLKCTL_CCSR]
+
+       /* make uart div=6 */
+       ldr r1, [r0, #CLKCTL_CSCDR1]
+       and r1, r1, #0xffffffc0
+       orr r1, r1, #0x0a
+       str r1, [r0, #CLKCTL_CSCDR1]
 
        /* Restore the default values in the Gate registers */
        ldr r1, =0xFFFFFFFF
@@ -322,50 +364,22 @@ setup_pll_func:
        str r1, [r0, #CLKCTL_CCGR6]
        str r1, [r0, #CLKCTL_CCGR7]
 
-       /* Switch peripheral to PLL2 */
-       ldr r0, =CCM_BASE_ADDR
-       ldr r1, =0x00808145
-       orr r1, r1, #2 << 10
-       orr r1, r1, #1 << 19
-       str r1, [r0, #CLKCTL_CBCDR]
-
-       ldr r1, =0x00016154
-       str r1, [r0, #CLKCTL_CBCMR]
-       /* Change uart clk parent to pll2*/
-       ldr r1, [r0, #CLKCTL_CSCMR1]
-       and r1, r1, #0xfcffffff
-       orr r1, r1, #0x01000000
-       str r1, [r0, #CLKCTL_CSCMR1]
-       ldr r1, [r0, #CLKCTL_CSCDR1]
-       and r1, r1, #0xffffffc0
-       orr r1, r1, #0x0a
-       str r1, [r0, #CLKCTL_CSCDR1]
-
-       /* make sure divider effective */
-1:     ldr r1, [r0, #CLKCTL_CDHIPR]
-       cmp r1, #0x0
-       bne 1b
-
-       str r4, [r0, #CLKCTL_CCDR]
+       mov r1, #0x00000
+       str r1, [r0, #CLKCTL_CCDR]
 
        /* for cko - for ARM div by 8 */
        mov r1, #0x000A0000
        add r1, r1, #0x00000F0
        str r1, [r0, #CLKCTL_CCOSR]
-#endif /* CONFIG_MX53 */
-.endm
 
-.macro setup_wdog
-       ldr r0, =WDOG1_BASE_ADDR
-       mov r1, #0x30
-       strh r1, [r0]
+#endif /* CONFIG_MX53 */
 .endm
 
 ENTRY(lowlevel_init)
        mov r10, lr
        mov r4, #0      /* Fix R4 to 0 */
 
-#if defined(CONFIG_MX51)
+#if defined(CONFIG_SYS_MAIN_PWR_ON)
        ldr r0, =GPIO1_BASE_ADDR
        ldr r1, [r0, #0x0]
        orr r1, r1, #1 << 23
@@ -375,6 +389,8 @@ ENTRY(lowlevel_init)
        str r1, [r0, #0x4]
 #endif
 
+       init_arm_erratum
+
        init_l2cc
 
        init_aips
@@ -405,3 +421,9 @@ W_DP_665:           .word DP_OP_665
 W_DP_216:              .word DP_OP_216
                        .word DP_MFD_216
                        .word DP_MFN_216
+W_DP_400:               .word DP_OP_400
+                       .word DP_MFD_400
+                       .word DP_MFN_400
+W_DP_455:               .word DP_OP_455
+                       .word DP_MFD_455
+                       .word DP_MFN_455