omap4: automatic sdram detection

[u-boot] / arch / arm / cpu / armv7 / mx5 / soc.c

diff --git a/arch/arm/cpu/armv7/mx5/soc.c b/arch/arm/cpu/armv7/mx5/soc.c
index 290011923eaf35699ddc9437f639702bf167de4b..c6106d5210651d1b25576c4b6c1144e3bbb1401b 100644 (file)
--- a/arch/arm/cpu/armv7/mx5/soc.c
+++ b/arch/arm/cpu/armv7/mx5/soc.c
@@ -33,17 +33,20 @@
 #include <fsl_esdhc.h>
 #endif
 
-#if defined(CONFIG_MX51)
-#define CPU_TYPE 0x51000
-#else
+#if !(defined(CONFIG_MX51) || defined(CONFIG_MX53))
 #error "CPU_TYPE not defined"
 #endif
 
 u32 get_cpu_rev(void)
 {
-       int system_rev = CPU_TYPE;
+#ifdef CONFIG_MX51
+       int system_rev = 0x51000;
+#else
+       int system_rev = 0x53000;
+#endif
        int reg = __raw_readl(ROM_SI_REV);
 
+#if defined(CONFIG_MX51)
        switch (reg) {
        case 0x02:
                system_rev |= CHIP_REV_1_1;
@@ -57,14 +60,46 @@ u32 get_cpu_rev(void)
        case 0x20:
                system_rev |= CHIP_REV_3_0;
                break;
-       return system_rev;
        default:
                system_rev |= CHIP_REV_1_0;
                break;
        }
+#else
+       if (reg < 0x20)
+               system_rev |= CHIP_REV_1_0;
+       else
+               system_rev |= reg;
+#endif
        return system_rev;
 }
 
+static char *get_reset_cause(void)
+{
+       u32 cause;
+       struct src *src_regs = (struct src *)SRC_BASE_ADDR;
+
+       cause = readl(&src_regs->srsr);
+       writel(cause, &src_regs->srsr);
+
+       switch (cause) {
+       case 0x00001:
+               return "POR";
+       case 0x00004:
+               return "CSU";
+       case 0x00008:
+               return "IPP USER";
+       case 0x00010:
+               return "WDOG";
+       case 0x00020:
+               return "JTAG HIGH-Z";
+       case 0x00040:
+               return "JTAG SW";
+       case 0x10000:
+               return "WARM BOOT";
+       default:
+               return "unknown reset";
+       }
+}
 
 #if defined(CONFIG_DISPLAY_CPUINFO)
 int print_cpuinfo(void)
@@ -77,6 +112,7 @@ int print_cpuinfo(void)
                (cpurev & 0x000F0) >> 4,
                (cpurev & 0x0000F) >> 0,
                mxc_get_clock(MXC_ARM_CLK) / 1000000);
+       printf("Reset cause: %s\n", get_reset_cause());
        return 0;
 }
 #endif
@@ -127,6 +163,36 @@ int cpu_mmc_init(bd_t *bis)
 #endif
 }
 
+void set_chipselect_size(int const cs_size)
+{
+       unsigned int reg;
+       struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
+       reg = readl(&iomuxc_regs->gpr1);
+
+       switch (cs_size) {
+       case CS0_128:
+               reg &= ~0x7;    /* CS0=128MB, CS1=0, CS2=0, CS3=0 */
+               reg |= 0x5;
+               break;
+       case CS0_64M_CS1_64M:
+               reg &= ~0x3F;   /* CS0=64MB, CS1=64MB, CS2=0, CS3=0 */
+               reg |= 0x1B;
+               break;
+       case CS0_64M_CS1_32M_CS2_32M:
+               reg &= ~0x1FF;  /* CS0=64MB, CS1=32MB, CS2=32MB, CS3=0 */
+               reg |= 0x4B;
+               break;
+       case CS0_32M_CS1_32M_CS2_32M_CS3_32M:
+               reg &= ~0xFFF;  /* CS0=32MB, CS1=32MB, CS2=32MB, CS3=32MB */
+               reg |= 0x249;
+               break;
+       default:
+               printf("Unknown chip select size: %d\n", cs_size);
+               break;
+       }
+
+       writel(reg, &iomuxc_regs->gpr1);
+}
 
 void reset_cpu(ulong addr)
 {