omap4: automatic sdram detection

[u-boot] / arch / arm / cpu / armv7 / mx5 / soc.c

diff --git a/arch/arm/cpu/armv7/mx5/soc.c b/arch/arm/cpu/armv7/mx5/soc.c
index 6f4e8db74d0ffa589e40274230b2fe93c465aa8e..c6106d5210651d1b25576c4b6c1144e3bbb1401b 100644 (file)
--- a/arch/arm/cpu/armv7/mx5/soc.c
+++ b/arch/arm/cpu/armv7/mx5/soc.c
@@ -65,14 +65,10 @@ u32 get_cpu_rev(void)
                break;
        }
 #else
-       switch (reg) {
-       case 0x20:
-               system_rev |= CHIP_REV_2_0;
-               break;
-       default:
+       if (reg < 0x20)
                system_rev |= CHIP_REV_1_0;
-               break;
-       }
+       else
+               system_rev |= reg;
 #endif
        return system_rev;
 }
@@ -167,6 +163,36 @@ int cpu_mmc_init(bd_t *bis)
 #endif
 }
 
+void set_chipselect_size(int const cs_size)
+{
+       unsigned int reg;
+       struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
+       reg = readl(&iomuxc_regs->gpr1);
+
+       switch (cs_size) {
+       case CS0_128:
+               reg &= ~0x7;    /* CS0=128MB, CS1=0, CS2=0, CS3=0 */
+               reg |= 0x5;
+               break;
+       case CS0_64M_CS1_64M:
+               reg &= ~0x3F;   /* CS0=64MB, CS1=64MB, CS2=0, CS3=0 */
+               reg |= 0x1B;
+               break;
+       case CS0_64M_CS1_32M_CS2_32M:
+               reg &= ~0x1FF;  /* CS0=64MB, CS1=32MB, CS2=32MB, CS3=0 */
+               reg |= 0x4B;
+               break;
+       case CS0_32M_CS1_32M_CS2_32M_CS3_32M:
+               reg &= ~0xFFF;  /* CS0=32MB, CS1=32MB, CS2=32MB, CS3=32MB */
+               reg |= 0x249;
+               break;
+       default:
+               printf("Unknown chip select size: %d\n", cs_size);
+               break;
+       }
+
+       writel(reg, &iomuxc_regs->gpr1);
+}
 
 void reset_cpu(ulong addr)
 {