omap4: automatic sdram detection

[u-boot] / arch / arm / cpu / armv7 / mx5 / timer.c

diff --git a/arch/arm/cpu/armv7/mx5/timer.c b/arch/arm/cpu/armv7/mx5/timer.c
index 3044fcf1e9bf1d7450e86a3d337a2812ab8fdb5b..2544b08761616dd9a847a18af20d4809acd1e157 100644 (file)
--- a/arch/arm/cpu/armv7/mx5/timer.c
+++ b/arch/arm/cpu/armv7/mx5/timer.c
@@ -44,12 +44,15 @@ static struct mxc_gpt *cur_gpt = (struct mxc_gpt *)GPT1_BASE_ADDR;
 #define GPTCR_CLKSOURCE_32 (4<<6)      /* Clock source */
 #define GPTCR_TEN       (1)    /* Timer enable */
 
-static ulong timestamp;
-static ulong lastinc;
+DECLARE_GLOBAL_DATA_PTR;
+
+#define timestamp (gd->tbl)
+#define lastinc (gd->lastinc)
 
 int timer_init(void)
 {
        int i;
+       ulong val;
 
        /* setup GP Timer 1 */
        __raw_writel(GPTCR_SWR, &cur_gpt->control);
@@ -63,20 +66,12 @@ int timer_init(void)
        /* Freerun Mode, PERCLK1 input */
        i = __raw_readl(&cur_gpt->control);
        __raw_writel(i | GPTCR_CLKSOURCE_32 | GPTCR_TEN, &cur_gpt->control);
-       reset_timer_masked();
-       return 0;
-}
 
-void reset_timer(void)
-{
-       reset_timer_masked();
-}
-
-void reset_timer_masked(void)
-{
-       ulong val = __raw_readl(&cur_gpt->counter);
+       val = __raw_readl(&cur_gpt->counter);
        lastinc = val / (CONFIG_SYS_MX5_CLK32 / CONFIG_SYS_HZ);
        timestamp = 0;
+
+       return 0;
 }
 
 ulong get_timer_masked(void)
@@ -97,11 +92,6 @@ ulong get_timer(ulong base)
        return get_timer_masked() - base;
 }
 
-void set_timer(ulong t)
-{
-       timestamp = t;
-}
-
 /* delay x useconds AND preserve advance timestamp value */
 void __udelay(unsigned long usec)
 {