Kconfig: Add CONFIG_SATA to enable SATA

[u-boot] / arch / arm / cpu / armv7 / mx6 / clock.c

diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c
index 007c135fd1d53e897af9f97865c65ecd5a119cd4..1f2739e8645e7806ae4fbaa8b5d614f2e0b20f4e 100644 (file)
--- a/arch/arm/cpu/armv7/mx6/clock.c
+++ b/arch/arm/cpu/armv7/mx6/clock.c
@@ -171,6 +171,8 @@ int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
                        reg &= ~mask;
                __raw_writel(reg, &imx_ccm->CCGR2);
        } else {
+               if (is_mx6sll())
+                       return -EINVAL;
                if (is_mx6sx() || is_mx6ul() || is_mx6ull()) {
                        mask = MXC_CCM_CCGR6_I2C4_MASK;
                        addr = &imx_ccm->CCGR6;
@@ -382,7 +384,7 @@ static u32 get_ipg_per_clk(void)
        u32 reg, perclk_podf;
 
        reg = __raw_readl(&imx_ccm->cscmr1);
-       if (is_mx6sl() || is_mx6sx() ||
+       if (is_mx6sll() || is_mx6sl() || is_mx6sx() ||
            is_mx6dqp() || is_mx6ul() || is_mx6ull()) {
                if (reg & MXC_CCM_CSCMR1_PER_CLK_SEL_MASK)
                        return MXC_HCLK; /* OSC 24Mhz */
@@ -400,7 +402,7 @@ static u32 get_uart_clk(void)
        reg = __raw_readl(&imx_ccm->cscdr1);
 
        if (is_mx6sl() || is_mx6sx() || is_mx6dqp() || is_mx6ul() ||
-           is_mx6ull()) {
+           is_mx6sll() || is_mx6ull()) {
                if (reg & MXC_CCM_CSCDR1_UART_CLK_SEL)
                        freq = MXC_HCLK;
        }
@@ -420,7 +422,7 @@ static u32 get_cspi_clk(void)
                     MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET;
 
        if (is_mx6dqp() || is_mx6sl() || is_mx6sx() || is_mx6ul() ||
-           is_mx6ull()) {
+           is_mx6sll() || is_mx6ull()) {
                if (reg & MXC_CCM_CSCDR2_ECSPI_CLK_SEL_MASK)
                        return MXC_HCLK / (cspi_podf + 1);
        }
@@ -482,7 +484,8 @@ static u32 get_mmdc_ch0_clk(void)
 
        u32 freq, podf, per2_clk2_podf, pmu_misc2_audio_div;
 
-       if (is_mx6sx() || is_mx6ul() || is_mx6ull() || is_mx6sl()) {
+       if (is_mx6sx() || is_mx6ul() || is_mx6ull() || is_mx6sl() ||
+           is_mx6sll()) {
                podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK) >>
                        MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET;
                if (cbcdr & MXC_CCM_CBCDR_PERIPH2_CLK_SEL) {
@@ -625,7 +628,8 @@ void mxs_set_lcdclk(u32 base_addr, u32 freq)
 
        debug("mxs_set_lcdclk, freq = %dKHz\n", freq);
 
-       if (!is_mx6sx() && !is_mx6ul() && !is_mx6ull() && !is_mx6sl()) {
+       if (!is_mx6sx() && !is_mx6ul() && !is_mx6ull() && !is_mx6sl() &&
+           !is_mx6sll()) {
                debug("This chip not support lcd!\n");
                return;
        }
@@ -707,6 +711,7 @@ void mxs_set_lcdclk(u32 base_addr, u32 freq)
                if (enable_pll_video(pll_div, pll_num, pll_denom, post_div))
                        return;
 
+               enable_lcdif_clock(base_addr, 0);
                if (!is_mx6sl()) {
                        /* Select pre-lcd clock to PLL5 and set pre divider */
                        clrsetbits_le32(&imx_ccm->cscdr2,
@@ -736,11 +741,14 @@ void mxs_set_lcdclk(u32 base_addr, u32 freq)
                                        (((postd - 1)^0x6) <<
                                         MXC_CCM_CSCMR1_LCDIF_PIX_PODF_OFFSET));
                }
+
+               enable_lcdif_clock(base_addr, 1);
        } else if (is_mx6sx()) {
                /* Setting LCDIF2 for i.MX6SX */
                if (enable_pll_video(pll_div, pll_num, pll_denom, post_div))
                        return;
 
+               enable_lcdif_clock(base_addr, 0);
                /* Select pre-lcd clock to PLL5 and set pre divider */
                clrsetbits_le32(&imx_ccm->cscdr2,
                                MXC_CCM_CSCDR2_LCDIF2_PRED_SEL_MASK |
@@ -754,10 +762,12 @@ void mxs_set_lcdclk(u32 base_addr, u32 freq)
                                MXC_CCM_CSCMR1_LCDIF2_PODF_MASK,
                                ((postd - 1) <<
                                 MXC_CCM_CSCMR1_LCDIF2_PODF_OFFSET));
+
+               enable_lcdif_clock(base_addr, 1);
        }
 }
 
-int enable_lcdif_clock(u32 base_addr)
+int enable_lcdif_clock(u32 base_addr, bool enable)
 {
        u32 reg = 0;
        u32 lcdif_clk_sel_mask, lcdif_ccgr3_mask;
@@ -777,7 +787,7 @@ int enable_lcdif_clock(u32 base_addr)
                         MXC_CCM_CCGR3_DISP_AXI_MASK) :
                        (MXC_CCM_CCGR3_LCDIF1_PIX_MASK |
                         MXC_CCM_CCGR3_DISP_AXI_MASK);
-       } else if (is_mx6ul() || is_mx6ull()) {
+       } else if (is_mx6ul() || is_mx6ull() || is_mx6sll()) {
                if (base_addr != LCDIF1_BASE_ADDR) {
                        puts("Wrong LCD interface!\n");
                        return -EINVAL;
@@ -796,15 +806,17 @@ int enable_lcdif_clock(u32 base_addr)
                         MXC_CCM_CCGR3_LCDIF_PIX_MASK);
                writel(reg, &imx_ccm->CCGR3);
 
-               reg = readl(&imx_ccm->cscdr3);
-               reg &= ~MXC_CCM_CSCDR3_LCDIF_AXI_CLK_SEL_MASK;
-               reg |= 1 << MXC_CCM_CSCDR3_LCDIF_AXI_CLK_SEL_OFFSET;
-               writel(reg, &imx_ccm->cscdr3);
+               if (enable) {
+                       reg = readl(&imx_ccm->cscdr3);
+                       reg &= ~MXC_CCM_CSCDR3_LCDIF_AXI_CLK_SEL_MASK;
+                       reg |= 1 << MXC_CCM_CSCDR3_LCDIF_AXI_CLK_SEL_OFFSET;
+                       writel(reg, &imx_ccm->cscdr3);
 
-               reg = readl(&imx_ccm->CCGR3);
-               reg |= MXC_CCM_CCGR3_LCDIF_AXI_MASK |
-                       MXC_CCM_CCGR3_LCDIF_PIX_MASK;
-               writel(reg, &imx_ccm->CCGR3);
+                       reg = readl(&imx_ccm->CCGR3);
+                       reg |= MXC_CCM_CCGR3_LCDIF_AXI_MASK |
+                               MXC_CCM_CCGR3_LCDIF_PIX_MASK;
+                       writel(reg, &imx_ccm->CCGR3);
+               }
 
                return 0;
        } else {
@@ -820,19 +832,21 @@ int enable_lcdif_clock(u32 base_addr)
        reg &= ~MXC_CCM_CCGR2_LCD_MASK;
        writel(reg, &imx_ccm->CCGR2);
 
-       /* Select pre-mux */
-       reg = readl(&imx_ccm->cscdr2);
-       reg &= ~lcdif_clk_sel_mask;
-       writel(reg, &imx_ccm->cscdr2);
+       if (enable) {
+               /* Select pre-mux */
+               reg = readl(&imx_ccm->cscdr2);
+               reg &= ~lcdif_clk_sel_mask;
+               writel(reg, &imx_ccm->cscdr2);
 
-       /* Enable the LCDIF pix clock */
-       reg = readl(&imx_ccm->CCGR3);
-       reg |= lcdif_ccgr3_mask;
-       writel(reg, &imx_ccm->CCGR3);
+               /* Enable the LCDIF pix clock */
+               reg = readl(&imx_ccm->CCGR3);
+               reg |= lcdif_ccgr3_mask;
+               writel(reg, &imx_ccm->CCGR3);
 
-       reg = readl(&imx_ccm->CCGR2);
-       reg |= MXC_CCM_CCGR2_LCD_MASK;
-       writel(reg, &imx_ccm->CCGR2);
+               reg = readl(&imx_ccm->CCGR2);
+               reg |= MXC_CCM_CCGR2_LCD_MASK;
+               writel(reg, &imx_ccm->CCGR2);
+       }
 
        return 0;
 }
@@ -971,6 +985,16 @@ static u32 get_usdhc_clk(u32 port)
        u32 cscmr1 = __raw_readl(&imx_ccm->cscmr1);
        u32 cscdr1 = __raw_readl(&imx_ccm->cscdr1);
 
+       if (is_mx6ul() || is_mx6ull()) {
+               if (port > 1)
+                       return 0;
+       }
+
+       if (is_mx6sll()) {
+               if (port > 2)
+                       return 0;
+       }
+
        switch (port) {
        case 0:
                usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC1_PODF_MASK) >>
@@ -1018,7 +1042,7 @@ u32 imx_get_fecclk(void)
        return mxc_get_clock(MXC_IPG_CLK);
 }
 
-#if defined(CONFIG_CMD_SATA) || defined(CONFIG_PCIE_IMX)
+#if defined(CONFIG_SATA) || defined(CONFIG_PCIE_IMX)
 static int enable_enet_pll(uint32_t en)
 {
        struct mxc_ccm_reg *const imx_ccm
@@ -1045,7 +1069,7 @@ static int enable_enet_pll(uint32_t en)
 }
 #endif
 
-#ifdef CONFIG_CMD_SATA
+#ifdef CONFIG_SATA
 static void ungate_sata_clock(void)
 {
        struct mxc_ccm_reg *const imx_ccm =
@@ -1119,7 +1143,7 @@ int enable_pcie_clock(void)
        clrbits_le32(&ccm_regs->cbcmr, MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL);
 
        /* Party time! Ungate the clock to the PCIe. */
-#ifdef CONFIG_CMD_SATA
+#ifdef CONFIG_SATA
        ungate_sata_clock();
 #endif
        ungate_pcie_clock();
@@ -1134,7 +1158,7 @@ void hab_caam_clock_enable(unsigned char enable)
 {
        u32 reg;
 
-       if (is_mx6ull()) {
+       if (is_mx6ull() || is_mx6sll()) {
                /* CG5, DCP clock */
                reg = __raw_readl(&imx_ccm->CCGR0);
                if (enable)
@@ -1439,7 +1463,7 @@ void select_ldb_di_clock_source(enum ldb_di_clock clk)
 }
 #endif
 
-#ifndef CONFIG_SYS_NO_FLASH
+#ifdef CONFIG_MTD_NOR_FLASH
 void enable_eim_clk(unsigned char enable)
 {
        u32 reg;