#include <common.h>
#include <div64.h>
#include <asm/io.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/clock.h>
{
u32 mask, *addr;
- if (is_mx6ul()) {
+ if (is_mx6ull()) {
+ mask = MXC_CCM_CCGR0_ENET_CLK_ENABLE_MASK;
+ addr = &imx_ccm->CCGR0;
+ } else if (is_mx6ul()) {
mask = MXC_CCM_CCGR3_ENET_MASK;
addr = &imx_ccm->CCGR3;
} else {
{
u32 mask;
- if (is_mx6ul())
+ if (is_mx6ul() || is_mx6ull())
mask = MXC_CCM_CCGR5_UART_MASK;
else
mask = MXC_CCM_CCGR5_UART_MASK | MXC_CCM_CCGR5_UART_SERIAL_MASK;
reg &= ~mask;
__raw_writel(reg, &imx_ccm->CCGR2);
} else {
- if (is_mx6sx() || is_mx6ul()) {
+ if (is_mx6sll())
+ return -EINVAL;
+ if (is_mx6sx() || is_mx6ul() || is_mx6ull()) {
mask = MXC_CCM_CCGR6_I2C4_MASK;
addr = &imx_ccm->CCGR6;
} else {
switch (pll) {
case PLL_BUS:
- if (!is_mx6ul()) {
+ if (!is_mx6ul() && !is_mx6ull()) {
if (pfd_num == 3) {
- /* No PFD3 on PPL2 */
+ /* No PFD3 on PLL2 */
return 0;
}
}
u32 reg, perclk_podf;
reg = __raw_readl(&imx_ccm->cscmr1);
- if (is_mx6sl() || is_mx6sx() ||
- is_mx6dqp() || is_mx6ul()) {
+ if (is_mx6sll() || is_mx6sl() || is_mx6sx() ||
+ is_mx6dqp() || is_mx6ul() || is_mx6ull()) {
if (reg & MXC_CCM_CSCMR1_PER_CLK_SEL_MASK)
return MXC_HCLK; /* OSC 24Mhz */
}
u32 freq = decode_pll(PLL_USBOTG, MXC_HCLK) / 6; /* static divider */
reg = __raw_readl(&imx_ccm->cscdr1);
- if (is_mx6sl() || is_mx6sx() || is_mx6dqp() || is_mx6ul()) {
+ if (is_mx6sl() || is_mx6sx() || is_mx6dqp() || is_mx6ul() ||
+ is_mx6sll() || is_mx6ull()) {
if (reg & MXC_CCM_CSCDR1_UART_CLK_SEL)
freq = MXC_HCLK;
}
cspi_podf = (reg & MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK) >>
MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET;
- if (is_mx6dqp() || is_mx6sl() || is_mx6sx() || is_mx6ul()) {
+ if (is_mx6dqp() || is_mx6sl() || is_mx6sx() || is_mx6ul() ||
+ is_mx6sll() || is_mx6ull()) {
if (reg & MXC_CCM_CSCDR2_ECSPI_CLK_SEL_MASK)
return MXC_HCLK / (cspi_podf + 1);
}
if (cbcdr & MXC_CCM_CBCDR_AXI_SEL) {
if (cbcdr & MXC_CCM_CBCDR_AXI_ALT_SEL)
- root_freq = mxc_get_pll_pfd(PLL_BUS, 2);
- else
root_freq = mxc_get_pll_pfd(PLL_USBOTG, 1);
+ else
+ root_freq = mxc_get_pll_pfd(PLL_BUS, 2);
} else
root_freq = get_periph_clk();
u32 freq, podf, per2_clk2_podf, pmu_misc2_audio_div;
- if (is_mx6sx() || is_mx6ul() || is_mx6sl()) {
+ if (is_mx6sx() || is_mx6ul() || is_mx6ull() || is_mx6sl() ||
+ is_mx6sll()) {
podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK) >>
MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET;
if (cbcdr & MXC_CCM_CBCDR_PERIPH2_CLK_SEL) {
freq = mxc_get_pll_pfd(PLL_BUS, 0);
break;
case 3:
+ if (is_mx6sl()) {
+ freq = mxc_get_pll_pfd(PLL_BUS, 2) >> 1;
+ break;
+ }
+
pmu_misc2_audio_div = PMU_MISC2_AUDIO_DIV(__raw_readl(&imx_ccm->pmu_misc2));
switch (pmu_misc2_audio_div) {
case 0:
debug("mxs_set_lcdclk, freq = %dKHz\n", freq);
- if (!is_mx6sx() && !is_mx6ul()) {
+ if (!is_mx6sx() && !is_mx6ul() && !is_mx6ull() && !is_mx6sl() &&
+ !is_mx6sll()) {
debug("This chip not support lcd!\n");
return;
}
- if (base_addr == LCDIF1_BASE_ADDR) {
- reg = readl(&imx_ccm->cscdr2);
- /* Can't change clocks when clock not from pre-mux */
- if ((reg & MXC_CCM_CSCDR2_LCDIF1_CLK_SEL_MASK) != 0)
- return;
+ if (!is_mx6sl()) {
+ if (base_addr == LCDIF1_BASE_ADDR) {
+ reg = readl(&imx_ccm->cscdr2);
+ /* Can't change clocks when clock not from pre-mux */
+ if ((reg & MXC_CCM_CSCDR2_LCDIF1_CLK_SEL_MASK) != 0)
+ return;
+ }
}
if (is_mx6sx()) {
if (enable_pll_video(pll_div, pll_num, pll_denom, post_div))
return;
- /* Select pre-lcd clock to PLL5 and set pre divider */
- clrsetbits_le32(&imx_ccm->cscdr2,
- MXC_CCM_CSCDR2_LCDIF1_PRED_SEL_MASK |
- MXC_CCM_CSCDR2_LCDIF1_PRE_DIV_MASK,
- (0x2 << MXC_CCM_CSCDR2_LCDIF1_PRED_SEL_OFFSET) |
- ((pred - 1) <<
- MXC_CCM_CSCDR2_LCDIF1_PRE_DIV_OFFSET));
+ enable_lcdif_clock(base_addr, 0);
+ if (!is_mx6sl()) {
+ /* Select pre-lcd clock to PLL5 and set pre divider */
+ clrsetbits_le32(&imx_ccm->cscdr2,
+ MXC_CCM_CSCDR2_LCDIF1_PRED_SEL_MASK |
+ MXC_CCM_CSCDR2_LCDIF1_PRE_DIV_MASK,
+ (0x2 << MXC_CCM_CSCDR2_LCDIF1_PRED_SEL_OFFSET) |
+ ((pred - 1) <<
+ MXC_CCM_CSCDR2_LCDIF1_PRE_DIV_OFFSET));
+
+ /* Set the post divider */
+ clrsetbits_le32(&imx_ccm->cbcmr,
+ MXC_CCM_CBCMR_LCDIF1_PODF_MASK,
+ ((postd - 1) <<
+ MXC_CCM_CBCMR_LCDIF1_PODF_OFFSET));
+ } else {
+ /* Select pre-lcd clock to PLL5 and set pre divider */
+ clrsetbits_le32(&imx_ccm->cscdr2,
+ MXC_CCM_CSCDR2_LCDIF_PIX_CLK_SEL_MASK |
+ MXC_CCM_CSCDR2_LCDIF_PIX_PRE_DIV_MASK,
+ (0x2 << MXC_CCM_CSCDR2_LCDIF_PIX_CLK_SEL_OFFSET) |
+ ((pred - 1) <<
+ MXC_CCM_CSCDR2_LCDIF_PIX_PRE_DIV_OFFSET));
+
+ /* Set the post divider */
+ clrsetbits_le32(&imx_ccm->cscmr1,
+ MXC_CCM_CSCMR1_LCDIF_PIX_PODF_MASK,
+ (((postd - 1)^0x6) <<
+ MXC_CCM_CSCMR1_LCDIF_PIX_PODF_OFFSET));
+ }
- /* Set the post divider */
- clrsetbits_le32(&imx_ccm->cbcmr,
- MXC_CCM_CBCMR_LCDIF1_PODF_MASK,
- ((postd - 1) <<
- MXC_CCM_CBCMR_LCDIF1_PODF_OFFSET));
+ enable_lcdif_clock(base_addr, 1);
} else if (is_mx6sx()) {
/* Setting LCDIF2 for i.MX6SX */
if (enable_pll_video(pll_div, pll_num, pll_denom, post_div))
return;
+ enable_lcdif_clock(base_addr, 0);
/* Select pre-lcd clock to PLL5 and set pre divider */
clrsetbits_le32(&imx_ccm->cscdr2,
MXC_CCM_CSCDR2_LCDIF2_PRED_SEL_MASK |
MXC_CCM_CSCMR1_LCDIF2_PODF_MASK,
((postd - 1) <<
MXC_CCM_CSCMR1_LCDIF2_PODF_OFFSET));
+
+ enable_lcdif_clock(base_addr, 1);
}
}
-int enable_lcdif_clock(u32 base_addr)
+int enable_lcdif_clock(u32 base_addr, bool enable)
{
u32 reg = 0;
u32 lcdif_clk_sel_mask, lcdif_ccgr3_mask;
MXC_CCM_CCGR3_DISP_AXI_MASK) :
(MXC_CCM_CCGR3_LCDIF1_PIX_MASK |
MXC_CCM_CCGR3_DISP_AXI_MASK);
- } else if (is_mx6ul()) {
+ } else if (is_mx6ul() || is_mx6ull() || is_mx6sll()) {
if (base_addr != LCDIF1_BASE_ADDR) {
puts("Wrong LCD interface!\n");
return -EINVAL;
/* Set to pre-mux clock at default */
lcdif_clk_sel_mask = MXC_CCM_CSCDR2_LCDIF1_CLK_SEL_MASK;
lcdif_ccgr3_mask = MXC_CCM_CCGR3_LCDIF1_PIX_MASK;
+ } else if (is_mx6sl()) {
+ if (base_addr != LCDIF1_BASE_ADDR) {
+ puts("Wrong LCD interface!\n");
+ return -EINVAL;
+ }
+
+ reg = readl(&imx_ccm->CCGR3);
+ reg &= ~(MXC_CCM_CCGR3_LCDIF_AXI_MASK |
+ MXC_CCM_CCGR3_LCDIF_PIX_MASK);
+ writel(reg, &imx_ccm->CCGR3);
+
+ if (enable) {
+ reg = readl(&imx_ccm->cscdr3);
+ reg &= ~MXC_CCM_CSCDR3_LCDIF_AXI_CLK_SEL_MASK;
+ reg |= 1 << MXC_CCM_CSCDR3_LCDIF_AXI_CLK_SEL_OFFSET;
+ writel(reg, &imx_ccm->cscdr3);
+
+ reg = readl(&imx_ccm->CCGR3);
+ reg |= MXC_CCM_CCGR3_LCDIF_AXI_MASK |
+ MXC_CCM_CCGR3_LCDIF_PIX_MASK;
+ writel(reg, &imx_ccm->CCGR3);
+ }
+
+ return 0;
} else {
return 0;
}
- reg = readl(&imx_ccm->cscdr2);
- reg &= ~lcdif_clk_sel_mask;
- writel(reg, &imx_ccm->cscdr2);
-
- /* Enable the LCDIF pix clock */
+ /* Gate LCDIF clock first */
reg = readl(&imx_ccm->CCGR3);
- reg |= lcdif_ccgr3_mask;
+ reg &= ~lcdif_ccgr3_mask;
writel(reg, &imx_ccm->CCGR3);
reg = readl(&imx_ccm->CCGR2);
- reg |= MXC_CCM_CCGR2_LCD_MASK;
+ reg &= ~MXC_CCM_CCGR2_LCD_MASK;
writel(reg, &imx_ccm->CCGR2);
+ if (enable) {
+ /* Select pre-mux */
+ reg = readl(&imx_ccm->cscdr2);
+ reg &= ~lcdif_clk_sel_mask;
+ writel(reg, &imx_ccm->cscdr2);
+
+ /* Enable the LCDIF pix clock */
+ reg = readl(&imx_ccm->CCGR3);
+ reg |= lcdif_ccgr3_mask;
+ writel(reg, &imx_ccm->CCGR3);
+
+ reg = readl(&imx_ccm->CCGR2);
+ reg |= MXC_CCM_CCGR2_LCD_MASK;
+ writel(reg, &imx_ccm->CCGR2);
+ }
+
return 0;
}
#endif
reg |= BF_ANADIG_PLL_ENET_DIV_SELECT(freq);
} else if (fec_id == 1) {
/* Only i.MX6SX/UL support ENET2 */
- if (!(is_mx6sx() || is_mx6ul()))
+ if (!(is_mx6sx() || is_mx6ul() || is_mx6ull()))
return -EINVAL;
reg &= ~BM_ANADIG_PLL_ENET2_DIV_SELECT;
reg |= BF_ANADIG_PLL_ENET2_DIV_SELECT(freq);
writel(reg, &anatop->pll_enet);
#ifdef CONFIG_MX6SX
+ /* Disable enet system clcok before switching clock parent */
+ reg = readl(&imx_ccm->CCGR3);
+ reg &= ~MXC_CCM_CCGR3_ENET_MASK;
+ writel(reg, &imx_ccm->CCGR3);
+
/*
* Set enet ahb clock to 200MHz
* pll2_pfd2_396m-> ENET_PODF-> ENET_AHB
u32 cscmr1 = __raw_readl(&imx_ccm->cscmr1);
u32 cscdr1 = __raw_readl(&imx_ccm->cscdr1);
+ if (is_mx6ul() || is_mx6ull()) {
+ if (port > 1)
+ return 0;
+ }
+
+ if (is_mx6sll()) {
+ if (port > 2)
+ return 0;
+ }
+
switch (port) {
case 0:
usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC1_PODF_MASK) >>
return mxc_get_clock(MXC_IPG_CLK);
}
-#if defined(CONFIG_CMD_SATA) || defined(CONFIG_PCIE_IMX)
+#if defined(CONFIG_SATA) || defined(CONFIG_PCIE_IMX)
static int enable_enet_pll(uint32_t en)
{
struct mxc_ccm_reg *const imx_ccm
}
#endif
-#ifdef CONFIG_CMD_SATA
+#ifdef CONFIG_SATA
static void ungate_sata_clock(void)
{
struct mxc_ccm_reg *const imx_ccm =
clrbits_le32(&ccm_regs->cbcmr, MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL);
/* Party time! Ungate the clock to the PCIe. */
-#ifdef CONFIG_CMD_SATA
+#ifdef CONFIG_SATA
ungate_sata_clock();
#endif
ungate_pcie_clock();
{
u32 reg;
- /* CG4 ~ CG6, CAAM clocks */
- reg = __raw_readl(&imx_ccm->CCGR0);
- if (enable)
- reg |= (MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK |
- MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK |
- MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK);
- else
- reg &= ~(MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK |
- MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK |
- MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK);
- __raw_writel(reg, &imx_ccm->CCGR0);
+ if (is_mx6ull() || is_mx6sll()) {
+ /* CG5, DCP clock */
+ reg = __raw_readl(&imx_ccm->CCGR0);
+ if (enable)
+ reg |= MXC_CCM_CCGR0_DCP_CLK_MASK;
+ else
+ reg &= ~MXC_CCM_CCGR0_DCP_CLK_MASK;
+ __raw_writel(reg, &imx_ccm->CCGR0);
+ } else {
+ /* CG4 ~ CG6, CAAM clocks */
+ reg = __raw_readl(&imx_ccm->CCGR0);
+ if (enable)
+ reg |= (MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK |
+ MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK |
+ MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK);
+ else
+ reg &= ~(MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK |
+ MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK |
+ MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK);
+ __raw_writel(reg, &imx_ccm->CCGR0);
+ }
/* EMI slow clk */
reg = __raw_readl(&imx_ccm->CCGR6);
}
#endif
+#ifdef CONFIG_MTD_NOR_FLASH
+void enable_eim_clk(unsigned char enable)
+{
+ u32 reg;
+
+ reg = __raw_readl(&imx_ccm->CCGR6);
+ if (enable)
+ reg |= MXC_CCM_CCGR6_EMI_SLOW_MASK;
+ else
+ reg &= ~MXC_CCM_CCGR6_EMI_SLOW_MASK;
+ __raw_writel(reg, &imx_ccm->CCGR6);
+}
+#endif
+
/***************************************************/
U_BOOT_CMD(
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