Merge branch 'master' of git://git.denx.de/u-boot-mpc5xxx

[u-boot] / arch / arm / cpu / armv7 / mx6 / clock.c

diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c
index ed2c913f05f39f74f0b646dbbfa3aac126e85243..3c0d908d179c9fd0fc79263950cc37a9fc6be76b 100644 (file)
--- a/arch/arm/cpu/armv7/mx6/clock.c
+++ b/arch/arm/cpu/armv7/mx6/clock.c
@@ -37,6 +37,20 @@ enum pll_clocks {
 
 struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 
+#ifdef CONFIG_MXC_OCOTP
+void enable_ocotp_clk(unsigned char enable)
+{
+       u32 reg;
+
+       reg = __raw_readl(&imx_ccm->CCGR2);
+       if (enable)
+               reg |= MXC_CCM_CCGR2_OCOTP_CTRL_MASK;
+       else
+               reg &= ~MXC_CCM_CCGR2_OCOTP_CTRL_MASK;
+       __raw_writel(reg, &imx_ccm->CCGR2);
+}
+#endif
+
 void enable_usboh3_clk(unsigned char enable)
 {
        u32 reg;
@@ -110,7 +124,7 @@ static u32 get_mcu_main_clk(void)
        reg = __raw_readl(&imx_ccm->cacrr);
        reg &= MXC_CCM_CACRR_ARM_PODF_MASK;
        reg >>= MXC_CCM_CACRR_ARM_PODF_OFFSET;
-       freq = decode_pll(PLL_SYS, CONFIG_SYS_MX6_HCLK);
+       freq = decode_pll(PLL_SYS, MXC_HCLK);
 
        return freq / (reg + 1);
 }
@@ -127,11 +141,11 @@ u32 get_periph_clk(void)
 
                switch (reg) {
                case 0:
-                       freq = decode_pll(PLL_USBOTG, CONFIG_SYS_MX6_HCLK);
+                       freq = decode_pll(PLL_USBOTG, MXC_HCLK);
                        break;
                case 1:
                case 2:
-                       freq = CONFIG_SYS_MX6_HCLK;
+                       freq = MXC_HCLK;
                        break;
                default:
                        break;
@@ -143,7 +157,7 @@ u32 get_periph_clk(void)
 
                switch (reg) {
                case 0:
-                       freq = decode_pll(PLL_BUS, CONFIG_SYS_MX6_HCLK);
+                       freq = decode_pll(PLL_BUS, MXC_HCLK);
                        break;
                case 1:
                        freq = PLL2_PFD2_FREQ;
@@ -186,12 +200,16 @@ static u32 get_ipg_per_clk(void)
 static u32 get_uart_clk(void)
 {
        u32 reg, uart_podf;
-
+       u32 freq = PLL3_80M;
        reg = __raw_readl(&imx_ccm->cscdr1);
+#ifdef CONFIG_MX6SL
+       if (reg & MXC_CCM_CSCDR1_UART_CLK_SEL)
+               freq = MXC_HCLK;
+#endif
        reg &= MXC_CCM_CSCDR1_UART_CLK_PODF_MASK;
        uart_podf = reg >> MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET;
 
-       return PLL3_80M / (uart_podf + 1);
+       return freq / (uart_podf + 1);
 }
 
 static u32 get_cspi_clk(void)
@@ -239,7 +257,7 @@ static u32 get_emi_slow_clk(void)
                root_freq = get_axi_clk();
                break;
        case 1:
-               root_freq = decode_pll(PLL_USBOTG, CONFIG_SYS_MX6_HCLK);
+               root_freq = decode_pll(PLL_USBOTG, MXC_HCLK);
                break;
        case 2:
                root_freq = PLL2_PFD2_FREQ;
@@ -252,6 +270,35 @@ static u32 get_emi_slow_clk(void)
        return root_freq / (emi_slow_pof + 1);
 }
 
+#ifdef CONFIG_MX6SL
+static u32 get_mmdc_ch0_clk(void)
+{
+       u32 cbcmr = __raw_readl(&imx_ccm->cbcmr);
+       u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
+       u32 freq, podf;
+
+       podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK) \
+                       >> MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET;
+
+       switch ((cbcmr & MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK) >>
+               MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET) {
+       case 0:
+               freq = decode_pll(PLL_BUS, MXC_HCLK);
+               break;
+       case 1:
+               freq = PLL2_PFD2_FREQ;
+               break;
+       case 2:
+               freq = PLL2_PFD0_FREQ;
+               break;
+       case 3:
+               freq = PLL2_PFD2_DIV_FREQ;
+       }
+
+       return freq / (podf + 1);
+
+}
+#else
 static u32 get_mmdc_ch0_clk(void)
 {
        u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
@@ -260,6 +307,7 @@ static u32 get_mmdc_ch0_clk(void)
 
        return get_periph_clk() / (mmdc_ch0_podf + 1);
 }
+#endif
 
 static u32 get_usdhc_clk(u32 port)
 {
@@ -311,7 +359,7 @@ u32 imx_get_uartclk(void)
 
 u32 imx_get_fecclk(void)
 {
-       return decode_pll(PLL_ENET, CONFIG_SYS_MX6_HCLK);
+       return decode_pll(PLL_ENET, MXC_HCLK);
 }
 
 int enable_sata_clock(void)
@@ -357,6 +405,7 @@ unsigned int mxc_get_clock(enum mxc_clock clk)
        case MXC_IPG_CLK:
                return get_ipg_clk();
        case MXC_IPG_PERCLK:
+       case MXC_I2C_CLK:
                return get_ipg_per_clk();
        case MXC_UART_CLK:
                return get_uart_clk();
@@ -391,19 +440,21 @@ unsigned int mxc_get_clock(enum mxc_clock clk)
 int do_mx6_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
        u32 freq;
-       freq = decode_pll(PLL_SYS, CONFIG_SYS_MX6_HCLK);
+       freq = decode_pll(PLL_SYS, MXC_HCLK);
        printf("PLL_SYS    %8d MHz\n", freq / 1000000);
-       freq = decode_pll(PLL_BUS, CONFIG_SYS_MX6_HCLK);
+       freq = decode_pll(PLL_BUS, MXC_HCLK);
        printf("PLL_BUS    %8d MHz\n", freq / 1000000);
-       freq = decode_pll(PLL_USBOTG, CONFIG_SYS_MX6_HCLK);
+       freq = decode_pll(PLL_USBOTG, MXC_HCLK);
        printf("PLL_OTG    %8d MHz\n", freq / 1000000);
-       freq = decode_pll(PLL_ENET, CONFIG_SYS_MX6_HCLK);
+       freq = decode_pll(PLL_ENET, MXC_HCLK);
        printf("PLL_NET    %8d MHz\n", freq / 1000000);
 
        printf("\n");
        printf("IPG        %8d kHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000);
        printf("UART       %8d kHz\n", mxc_get_clock(MXC_UART_CLK) / 1000);
+#ifdef CONFIG_MXC_SPI
        printf("CSPI       %8d kHz\n", mxc_get_clock(MXC_CSPI_CLK) / 1000);
+#endif
        printf("AHB        %8d kHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000);
        printf("AXI        %8d kHz\n", mxc_get_clock(MXC_AXI_CLK) / 1000);
        printf("DDR        %8d kHz\n", mxc_get_clock(MXC_DDR_CLK) / 1000);