Merge branch 'next' of git://git.denx.de/u-boot-mpc83xx

[u-boot] / arch / arm / cpu / armv7 / mx6 / clock.c

diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c
index 7a29c9b6921e3732cab5fd57530590c194e07e03..df11678609b060b75af3ae12b13a8cca94c75b6c 100644 (file)
--- a/arch/arm/cpu/armv7/mx6/clock.c
+++ b/arch/arm/cpu/armv7/mx6/clock.c
@@ -282,6 +282,36 @@ static u32 get_mmdc_ch0_clk(void)
        return freq / (podf + 1);
 
 }
+
+int enable_fec_anatop_clock(void)
+{
+       u32 reg = 0;
+       s32 timeout = 100000;
+
+       struct anatop_regs __iomem *anatop =
+               (struct anatop_regs __iomem *)ANATOP_BASE_ADDR;
+
+       reg = readl(&anatop->pll_enet);
+       if ((reg & BM_ANADIG_PLL_ENET_POWERDOWN) ||
+           (!(reg & BM_ANADIG_PLL_ENET_LOCK))) {
+               reg &= ~BM_ANADIG_PLL_ENET_POWERDOWN;
+               writel(reg, &anatop->pll_enet);
+               while (timeout--) {
+                       if (readl(&anatop->pll_enet) & BM_ANADIG_PLL_ENET_LOCK)
+                               break;
+               }
+               if (timeout < 0)
+                       return -ETIMEDOUT;
+       }
+
+       /* Enable FEC clock */
+       reg |= BM_ANADIG_PLL_ENET_ENABLE;
+       reg &= ~BM_ANADIG_PLL_ENET_BYPASS;
+       writel(reg, &anatop->pll_enet);
+
+       return 0;
+}
+
 #else
 static u32 get_mmdc_ch0_clk(void)
 {
@@ -457,7 +487,7 @@ void enable_ipu_clock(void)
        struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
        int reg;
        reg = readl(&mxc_ccm->CCGR3);
-       reg |= MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET;
+       reg |= MXC_CCM_CCGR3_IPU1_IPU_MASK;
        writel(reg, &mxc_ccm->CCGR3);
 }
 /***************************************************/