Merge branch 'master' of git://www.denx.de/git/u-boot-imx

[u-boot] / arch / arm / cpu / armv7 / mx6 / soc.c

diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c
index 63524222539134df5c69c6b2179a334850199ec4..ef029722b455d7c12012de2d6178d7a58e146dd6 100644 (file)
--- a/arch/arm/cpu/armv7/mx6/soc.c
+++ b/arch/arm/cpu/armv7/mx6/soc.c
@@ -9,6 +9,7 @@
 
 #include <common.h>
 #include <asm/armv7.h>
+#include <asm/bootm.h>
 #include <asm/pl310.h>
 #include <asm/errno.h>
 #include <asm/io.h>
@@ -20,6 +21,9 @@
 #include <stdbool.h>
 #include <asm/arch/mxc_hdmi.h>
 #include <asm/arch/crm_regs.h>
+#include <asm/bootm.h>
+#include <dm.h>
+#include <imx_thermal.h>
 
 enum ldo_reg {
        LDO_ARM,
@@ -35,6 +39,19 @@ struct scu_regs {
        u32     fpga_rev;
 };
 
+#if defined(CONFIG_IMX6_THERMAL)
+static const struct imx_thermal_plat imx6_thermal_plat = {
+       .regs = (void *)ANATOP_BASE_ADDR,
+       .fuse_bank = 1,
+       .fuse_word = 6,
+};
+
+U_BOOT_DEVICE(imx6_thermal) = {
+       .name = "imx_thermal",
+       .platdata = &imx6_thermal_plat,
+};
+#endif
+
 u32 get_nr_cpus(void)
 {
        struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR;
@@ -92,7 +109,7 @@ void init_aips(void)
        aips1 = (struct aipstz_regs *)AIPS1_BASE_ADDR;
        aips2 = (struct aipstz_regs *)AIPS2_BASE_ADDR;
 #ifdef CONFIG_MX6SX
-       aips3 = (struct aipstz_regs *)AIPS3_BASE_ADDR;
+       aips3 = (struct aipstz_regs *)AIPS3_CONFIG_BASE_ADDR;
 #endif
 
        /*
@@ -213,6 +230,11 @@ static void imx_set_wdog_powerdown(bool enable)
        struct wdog_regs *wdog1 = (struct wdog_regs *)WDOG1_BASE_ADDR;
        struct wdog_regs *wdog2 = (struct wdog_regs *)WDOG2_BASE_ADDR;
 
+#ifdef CONFIG_MX6SX
+       struct wdog_regs *wdog3 = (struct wdog_regs *)WDOG3_BASE_ADDR;
+       writew(enable, &wdog3->wmcr);
+#endif
+
        /* Write to the PDE (Power Down Enable) bit */
        writew(enable, &wdog1->wmcr);
        writew(enable, &wdog2->wmcr);
@@ -238,6 +260,35 @@ static void clear_mmdc_ch_mask(void)
        writel(0, &mxc_ccm->ccdr);
 }
 
+static void init_bandgap(void)
+{
+       struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
+       /*
+        * Ensure the bandgap has stabilized.
+        */
+       while (!(readl(&anatop->ana_misc0) & 0x80))
+               ;
+       /*
+        * For best noise performance of the analog blocks using the
+        * outputs of the bandgap, the reftop_selfbiasoff bit should
+        * be set.
+        */
+       writel(BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF, &anatop->ana_misc0_set);
+}
+
+
+#ifdef CONFIG_MX6SL
+static void set_preclk_from_osc(void)
+{
+       struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+       u32 reg;
+
+       reg = readl(&mxc_ccm->cscmr1);
+       reg |= MXC_CCM_CSCMR1_PER_CLK_SEL_MASK;
+       writel(reg, &mxc_ccm->cscmr1);
+}
+#endif
+
 int arch_cpu_init(void)
 {
        init_aips();
@@ -245,6 +296,13 @@ int arch_cpu_init(void)
        /* Need to clear MMDC_CHx_MASK to make warm reset work. */
        clear_mmdc_ch_mask();
 
+       /*
+        * Disable self-bias circuit in the analog bandap.
+        * The self-bias circuit is used by the bandgap during startup.
+        * This bit should be set after the bandgap has initialized.
+        */
+       init_bandgap();
+
        /*
         * When low freq boot is enabled, ROM will not set AHB
         * freq, so we need to ensure AHB freq is 132MHz in such
@@ -253,6 +311,11 @@ int arch_cpu_init(void)
        if (mxc_get_clock(MXC_ARM_CLK) == 396000000)
                set_ahb_rate(132000000);
 
+               /* Set perclk to source from OSC 24MHz */
+#if defined(CONFIG_MX6SL)
+       set_preclk_from_osc();
+#endif
+
        imx_set_wdog_powerdown(false); /* Disable PDE bit of WMCR register */
 
 #ifdef CONFIG_APBH_DMA
@@ -331,8 +394,8 @@ void boot_mode_apply(unsigned cfg_val)
 /*
  * cfg_val will be used for
  * Boot_cfg4[7:0]:Boot_cfg3[7:0]:Boot_cfg2[7:0]:Boot_cfg1[7:0]
- * After reset, if GPR10[28] is 1, ROM will copy GPR9[25:0]
- * to SBMR1, which will determine the boot device.
+ * After reset, if GPR10[28] is 1, ROM will use GPR9[25:0]
+ * instead of SBMR1 to determine the boot device.
  */
 const struct boot_mode soc_boot_modes[] = {
        {"normal",      MAKE_CFGVAL(0x00, 0x00, 0x00, 0x00)},