Merge git://git.denx.de/u-boot-spi

[u-boot] / arch / arm / cpu / armv7 / nonsec_virt.S

diff --git a/arch/arm/cpu/armv7/nonsec_virt.S b/arch/arm/cpu/armv7/nonsec_virt.S
index 30d81db8b81b398905249b5fff4b0fc218fa6109..e39aba711587ecafabb8457d6c34bde1abb42353 100644 (file)
--- a/arch/arm/cpu/armv7/nonsec_virt.S
+++ b/arch/arm/cpu/armv7/nonsec_virt.S
@@ -37,7 +37,7 @@ _monitor_vectors:
 
 /*
  * secure monitor handler
- * U-boot calls this "software interrupt" in start.S
+ * U-Boot calls this "software interrupt" in start.S
  * This is executed on a "smc" instruction, we use a "smc #0" to switch
  * to non-secure state.
  * r0, r1, r2: passed to the callee
@@ -49,8 +49,27 @@ _secure_monitor:
        mcr     p15, 0, r5, c12, c0, 1
        isb
 
-       @ Obtain a secure stack, and configure the PSCI backend
+       @ Obtain a secure stack
+       bl      psci_stack_setup
+
+       @ Configure the PSCI backend
+       push    {r0, r1, r2, ip}
        bl      psci_arch_init
+       pop     {r0, r1, r2, ip}
+#endif
+
+#ifdef CONFIG_ARM_ERRATA_773022
+       mrc     p15, 0, r5, c1, c0, 1
+       orr     r5, r5, #(1 << 1)
+       mcr     p15, 0, r5, c1, c0, 1
+       isb
+#endif
+
+#ifdef CONFIG_ARM_ERRATA_774769
+       mrc     p15, 0, r5, c1, c0, 1
+       orr     r5, r5, #(1 << 25)
+       mcr     p15, 0, r5, c1, c0, 1
+       isb
 #endif
 
        mrc     p15, 0, r5, c1, c1, 0           @ read SCR
@@ -169,11 +188,11 @@ ENTRY(_nonsec_init)
  * we do this here instead.
  * But first check if we have the generic timer.
  */
-#ifdef CONFIG_TIMER_CLK_FREQ
+#ifdef COUNTER_FREQUENCY
        mrc     p15, 0, r0, c0, c1, 1           @ read ID_PFR1
        and     r0, r0, #CPUID_ARM_GENTIMER_MASK        @ mask arch timer bits
        cmp     r0, #(1 << CPUID_ARM_GENTIMER_SHIFT)
-       ldreq   r1, =CONFIG_TIMER_CLK_FREQ
+       ldreq   r1, =COUNTER_FREQUENCY
        mcreq   p15, 0, r1, c14, c0, 0          @ write CNTFRQ
 #endif