#include <asm/arch/clock.h>
#include <asm/arch/sys_proto.h>
#include <asm/omap_common.h>
+#include <asm/omap_sec_common.h>
#include <asm/utils.h>
#include <linux/compiler.h>
void force_emif_self_refresh()
{
set_lpmode_selfrefresh(EMIF1_BASE);
- set_lpmode_selfrefresh(EMIF2_BASE);
+ if (!is_dra72x())
+ set_lpmode_selfrefresh(EMIF2_BASE);
}
inline u32 emif_num(u32 base)
}
}
+#ifndef CONFIG_OMAP44XX
static void omap5_ddr3_leveling(u32 base, const struct emif_regs *regs)
{
struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
else
dra7_ddr3_init(base, regs);
}
+#endif
#ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
#define print_timing_reg(reg) debug(#reg" - 0x%08x\n", (reg))
#endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */
/*
- * Initializing the LPDDR2 device can not happen from SDRAM.
+ * Initializing the DDR device can not happen from SDRAM.
* Changing the timing registers in EMIF can happen(going from one
* OPP to another)
*/
if (emif_sdram_type(regs->sdram_config) ==
EMIF_SDRAM_TYPE_LPDDR2)
lpddr2_init(base, regs);
+#ifndef CONFIG_OMAP44XX
else
ddr3_init(base, regs);
+#endif
}
+#ifdef CONFIG_OMAP54X
if (warm_reset() && (emif_sdram_type(regs->sdram_config) ==
EMIF_SDRAM_TYPE_DDR3) && !is_dra7xx()) {
set_lpmode_selfrefresh(base);
emif_reset_phy(base);
omap5_ddr3_leveling(base, regs);
}
+#endif
/* Write to the shadow registers */
emif_update_timings(base, regs);
debug("get_ram_size() successful");
}
+#if defined(CONFIG_TI_SECURE_DEVICE)
+ /*
+ * On HS devices, do static EMIF firewall configuration
+ * but only do it if not already running in SDRAM
+ */
+ if (!in_sdram)
+ if (0 != secure_emif_reserve())
+ hang();
+
+ /* On HS devices, ensure static EMIF firewall APIs are locked */
+ if (0 != secure_emif_firewall_lock())
+ hang();
+#endif
+
if (sdram_type == EMIF_SDRAM_TYPE_DDR3 &&
(!in_sdram && !warm_reset()) && (!is_dra7xx())) {
if (emif1_enabled)