arm: Introduce ARCH_OMAP2

[u-boot] / arch / arm / cpu / armv7 / omap-common / emif-common.c

diff --git a/arch/arm/cpu/armv7/omap-common/emif-common.c b/arch/arm/cpu/armv7/omap-common/emif-common.c
index 697d6e02dae5999f1de95f7d82d019522dad1f08..b26984e26c5e8648598a36380d991fb34d1dd3df 100644 (file)
--- a/arch/arm/cpu/armv7/omap-common/emif-common.c
+++ b/arch/arm/cpu/armv7/omap-common/emif-common.c
@@ -14,6 +14,7 @@
 #include <asm/arch/clock.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/omap_common.h>
+#include <asm/omap_sec_common.h>
 #include <asm/utils.h>
 #include <linux/compiler.h>
 
@@ -37,7 +38,8 @@ void set_lpmode_selfrefresh(u32 base)
 void force_emif_self_refresh()
 {
        set_lpmode_selfrefresh(EMIF1_BASE);
-       set_lpmode_selfrefresh(EMIF2_BASE);
+       if (!is_dra72x())
+               set_lpmode_selfrefresh(EMIF2_BASE);
 }
 
 inline u32 emif_num(u32 base)
@@ -195,6 +197,7 @@ void emif_update_timings(u32 base, const struct emif_regs *regs)
        }
 }
 
+#ifndef CONFIG_OMAP44XX
 static void omap5_ddr3_leveling(u32 base, const struct emif_regs *regs)
 {
        struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
@@ -405,6 +408,7 @@ static void ddr3_init(u32 base, const struct emif_regs *regs)
        else
                dra7_ddr3_init(base, regs);
 }
+#endif
 
 #ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
 #define print_timing_reg(reg) debug(#reg" - 0x%08x\n", (reg))
@@ -1178,7 +1182,7 @@ static void do_sdram_init(u32 base)
 #endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */
 
        /*
-        * Initializing the LPDDR2 device can not happen from SDRAM.
+        * Initializing the DDR device can not happen from SDRAM.
         * Changing the timing registers in EMIF can happen(going from one
         * OPP to another)
         */
@@ -1186,15 +1190,19 @@ static void do_sdram_init(u32 base)
                if (emif_sdram_type(regs->sdram_config) ==
                    EMIF_SDRAM_TYPE_LPDDR2)
                        lpddr2_init(base, regs);
+#ifndef CONFIG_OMAP44XX
                else
                        ddr3_init(base, regs);
+#endif
        }
+#ifdef CONFIG_OMAP54X
        if (warm_reset() && (emif_sdram_type(regs->sdram_config) ==
            EMIF_SDRAM_TYPE_DDR3) && !is_dra7xx()) {
                set_lpmode_selfrefresh(base);
                emif_reset_phy(base);
                omap5_ddr3_leveling(base, regs);
        }
+#endif
 
        /* Write to the shadow registers */
        emif_update_timings(base, regs);
@@ -1470,6 +1478,20 @@ void sdram_init(void)
                        debug("get_ram_size() successful");
        }
 
+#if defined(CONFIG_TI_SECURE_DEVICE)
+       /*
+        * On HS devices, do static EMIF firewall configuration
+        * but only do it if not already running in SDRAM
+        */
+       if (!in_sdram)
+               if (0 != secure_emif_reserve())
+                       hang();
+
+       /* On HS devices, ensure static EMIF firewall APIs are locked */
+       if (0 != secure_emif_firewall_lock())
+               hang();
+#endif
+
        if (sdram_type == EMIF_SDRAM_TYPE_DDR3 &&
            (!in_sdram && !warm_reset()) && (!is_dra7xx())) {
                if (emif1_enabled)